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f63be7d395
XMM registers. There are many known deficiencies and fixmes, which will be
addressed ASAP. The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.
The x86 backend will still default to x87 style FP. To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.
An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
Sum += P[i]; return Sum; }
The inner loop looks like the following:
x87:
.LBB_foo_1: # no_exit
fldl (%esp)
faddl (%eax,%ecx,8)
fstpl (%esp)
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
SSE2:
addsd (%eax,%ecx,8), %xmm0
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22340 91177308-0d34-0410-b5e6-96231b3b80d8
74 lines
2.3 KiB
C++
74 lines
2.3 KiB
C++
//===- X86.td - Target definition file for the Intel X86 arch ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is a target description file for the Intel i386 architecture, refered to
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// here as the "X86" architecture.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing...
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//
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include "../Target.td"
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "X86RegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "X86InstrInfo.td"
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def X86InstrInfo : InstrInfo {
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let PHIInst = PHI;
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// Define how we want to layout our TargetSpecific information field... This
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// should be kept up-to-date with the fields in the X86InstrInfo.h file.
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let TSFlagsFields = ["FormBits",
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"hasOpSizePrefix",
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"Prefix",
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"ImmTypeBits",
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"FPFormBits",
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"Opcode"];
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let TSFlagsShifts = [0,
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5,
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6,
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10,
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12,
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16];
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}
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// The X86 target supports two different syntaxes for emitting machine code.
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// This is controlled by the -x86-asm-syntax={att|intel}
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def ATTAsmWriter : AsmWriter {
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string AsmWriterClassName = "ATTAsmPrinter";
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int Variant = 0;
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}
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def IntelAsmWriter : AsmWriter {
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string AsmWriterClassName = "IntelAsmPrinter";
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int Variant = 1;
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}
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def X86 : Target {
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// Specify the callee saved registers.
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let CalleeSavedRegisters = [ESI, EDI, EBX, EBP, XMM4, XMM5, XMM6, XMM7];
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// Yes, pointers are 32-bits in size.
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let PointerType = i32;
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// Information about the instructions...
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let InstructionSet = X86InstrInfo;
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let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
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}
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