Chad Rosier 743e19983e [fast-isel] Add support for SUBs with non-legal types. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150047 91177308-0d34-0410-b5e6-96231b3b80d8

2012-02-08 02:45:44 +00:00

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ARM

[fast-isel] Add support for SUBs with non-legal types.

2012-02-08 02:45:44 +00:00

CBackend

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CellSPU

Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.

2012-01-17 21:44:01 +00:00

CPP

Testcase for commit 149833 (use of an uninitialized variable noticed

2012-02-05 19:27:57 +00:00

Generic

Move test/CodeGen/Generic/2012-02-01-CoalescerBug.ll to CodeGen/ARM, for now. It requires TARGETS=arm.

2012-02-02 11:44:58 +00:00

Hexagon

VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).

2012-02-01 22:13:57 +00:00

MBlaze

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Mips

Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is

2012-02-03 04:33:00 +00:00

MSP430

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PowerPC

AggressiveAntiDepBreaker needs to skip debug values because a debug value does not have a corresponding SUnit

2012-01-16 22:53:41 +00:00

PTX

PTX: Continue to fix up the register mess.

2011-12-06 17:39:48 +00:00

SPARC

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Thumb

Fix more places which should be checking for iOS, not darwin.

2012-01-04 01:55:04 +00:00

Thumb2

After r147827 and r147902, it's now possible for unallocatable registers to be

2012-01-14 01:53:46 +00:00

X86

Add instruction selection for 256-bit VPSHUFD and 128-bit VPERMILPS/VPERMILPD.

2012-02-07 06:28:42 +00:00

XCore

FileCheck hygiene.

2012-01-05 00:43:34 +00:00