Dan Gohman 74692c0d65 Whitespace tidiments. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62963 91177308-0d34-0410-b5e6-96231b3b80d8

2009-01-25 16:21:38 +00:00

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CallingConvLower.cpp

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CMakeLists.txt

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DAGCombiner.cpp

Fold x-0 to x in unsafe-fp-math mode. This comes up in the

2009-01-23 19:10:37 +00:00

FastISel.cpp

Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.

2009-01-22 09:10:11 +00:00

LegalizeDAG.cpp

Fix an indent and a typo.

2009-01-24 22:12:48 +00:00

LegalizeFloatTypes.cpp

Cleanup whitespace and comments, and tweak some

2009-01-21 09:00:29 +00:00

LegalizeIntegerTypes.cpp

Cleanup whitespace and comments, and tweak some

2009-01-21 09:00:29 +00:00

LegalizeTypes.cpp

Cleanup whitespace and comments, and tweak some

2009-01-21 09:00:29 +00:00

LegalizeTypes.h

Cleanup whitespace and comments, and tweak some

2009-01-21 09:00:29 +00:00

LegalizeTypesGeneric.cpp

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LegalizeVectorTypes.cpp

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Makefile

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ScheduleDAGFast.cpp

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ScheduleDAGList.cpp

Initial hazard recognizer support in post-pass scheduling. This includes

2009-01-16 01:33:36 +00:00

ScheduleDAGRRList.cpp

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ScheduleDAGSDNodes.cpp

CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions.

2009-01-16 20:57:18 +00:00

ScheduleDAGSDNodesEmit.cpp

Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.

2009-01-22 09:10:11 +00:00

SelectionDAG.cpp

Whitespace tidiments.

2009-01-25 16:21:38 +00:00

SelectionDAGBuild.cpp

Cleanup whitespace and comments, and tweak some

2009-01-21 09:00:29 +00:00

SelectionDAGBuild.h

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SelectionDAGISel.cpp

Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.

2009-01-20 19:12:24 +00:00

SelectionDAGPrinter.cpp

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TargetLowering.cpp

Add SelectionDAG::getNOT method to construct bitwise NOT operations,

2009-01-22 17:39:32 +00:00