mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-06 23:32:27 +00:00
4da992aeba
mostly based on the ARM AsmParser at this time and is not particularly
functional.
Changed the MBlaze data layout from:
"E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32"
to:
"E-p:32:32:32-i8:8:8-i16:16:16"
because the MicroBlaze doesn't have i64, f64, v64, or v128 data types.
Cleaned up the MBlaze source code:
1. The floating point register class has been removed. The
MicroBlaze does not have floating point registers. Floating
point values are simply stored in integer registers.
2. Renaming the CPURegs register class to GPR to reflect the
standard naming.
3. Removing a lot of stale code from AsmPrinter after
the conversion to InstPrinter.
4. Simplified sign extended loads by marking them as
expanded in ISelLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117054 91177308-0d34-0410-b5e6-96231b3b80d8
218 lines
11 KiB
TableGen
218 lines
11 KiB
TableGen
//===- MBlazeInstrFSL.td - MBlaze FSL Instruction defs -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// FSL Instruction Formats
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//===----------------------------------------------------------------------===//
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class FSLGet<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> :
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MBlazeInst<op, FFSL, (outs GPR:$dst), (ins fslimm:$b),
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!strconcat(instr_asm, " $dst, $b"),
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[(set GPR:$dst, (OpNode immZExt4:$b))],IIAlu>
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{
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bits<5> rd;
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bits<4> fslno;
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let Inst{6-10} = rd;
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let Inst{11-15} = 0x0;
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let Inst{16} = 0x0;
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let Inst{17-21} = flags; // NCTAE
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let Inst{22-27} = 0x0;
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let Inst{28-31} = fslno;
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}
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class FSLGetD<bits<6> op, bits<5> flags, string instr_asm, Intrinsic OpNode> :
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MBlazeInst<op, FFSLD, (outs GPR:$dst), (ins GPR:$b),
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!strconcat(instr_asm, " $dst, $b"),
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[(set GPR:$dst, (OpNode GPR:$b))], IIAlu>
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{
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bits<5> rd;
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bits<5> rb;
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let Inst{6-10} = rd;
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let Inst{11-15} = 0x0;
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let Inst{16-20} = rb;
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let Inst{21} = 0x0;
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let Inst{22-26} = flags; // NCTAE
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let Inst{27-31} = 0x0;
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}
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class FSLPut<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
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MBlazeInst<op, FFSL, (outs), (ins GPR:$v, fslimm:$b),
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!strconcat(instr_asm, " $v, $b"),
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[(OpNode GPR:$v, immZExt4:$b)], IIAlu>
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{
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bits<5> ra;
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bits<4> fslno;
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let Inst{6-10} = 0x0;
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let Inst{11-15} = ra;
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let Inst{16} = 0x1;
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let Inst{17-20} = flags; // NCTA
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let Inst{21-27} = 0x0;
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let Inst{28-31} = fslno;
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}
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class FSLPutD<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
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MBlazeInst<op, FFSLD, (outs), (ins GPR:$v, GPR:$b),
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!strconcat(instr_asm, " $v, $b"),
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[(OpNode GPR:$v, GPR:$b)], IIAlu>
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{
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bits<5> ra;
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bits<5> rb;
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let Inst{6-10} = 0x0;
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let Inst{11-15} = ra;
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let Inst{16-20} = rb;
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let Inst{21} = 0x1;
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let Inst{22-25} = flags; // NCTA
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let Inst{26-31} = 0x0;
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}
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class FSLPutT<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
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MBlazeInst<op, FFSLT, (outs), (ins fslimm:$b),
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!strconcat(instr_asm, " $b"),
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[(OpNode immZExt4:$b)], IIAlu>
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{
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bits<4> fslno;
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let Inst{6-10} = 0x0;
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let Inst{11-15} = 0x0;
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let Inst{16} = 0x1;
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let Inst{17-20} = flags; // NCTA
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let Inst{21-27} = 0x0;
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let Inst{28-31} = fslno;
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}
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class FSLPutTD<bits<6> op, bits<4> flags, string instr_asm, Intrinsic OpNode> :
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MBlazeInst<op, FFSLTD, (outs), (ins GPR:$b),
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!strconcat(instr_asm, " $b"),
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[(OpNode GPR:$b)], IIAlu>
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{
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bits<5> rb;
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let Inst{6-10} = 0x0;
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let Inst{11-15} = 0x0;
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let Inst{16-20} = rb;
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let Inst{21} = 0x1;
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let Inst{22-25} = flags; // NCTA
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let Inst{26-31} = 0x0;
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}
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//===----------------------------------------------------------------------===//
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// FSL Get Instructions
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//===----------------------------------------------------------------------===//
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def GET : FSLGet<0x1B, 0x00, "get ", int_mblaze_fsl_get>;
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def AGET : FSLGet<0x1B, 0x02, "aget ", int_mblaze_fsl_aget>;
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def CGET : FSLGet<0x1B, 0x08, "cget ", int_mblaze_fsl_cget>;
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def CAGET : FSLGet<0x1B, 0x0A, "caget ", int_mblaze_fsl_caget>;
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def EGET : FSLGet<0x1B, 0x01, "eget ", int_mblaze_fsl_eget>;
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def EAGET : FSLGet<0x1B, 0x03, "eaget ", int_mblaze_fsl_eaget>;
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def ECGET : FSLGet<0x1B, 0x09, "ecget ", int_mblaze_fsl_ecget>;
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def ECAGET : FSLGet<0x1B, 0x0B, "ecaget ", int_mblaze_fsl_ecaget>;
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def NGET : FSLGet<0x1B, 0x10, "nget ", int_mblaze_fsl_nget>;
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def NAGET : FSLGet<0x1B, 0x12, "naget ", int_mblaze_fsl_naget>;
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def NCGET : FSLGet<0x1B, 0x18, "ncget ", int_mblaze_fsl_ncget>;
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def NCAGET : FSLGet<0x1B, 0x1A, "ncaget ", int_mblaze_fsl_ncaget>;
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def NEGET : FSLGet<0x1B, 0x11, "neget ", int_mblaze_fsl_neget>;
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def NEAGET : FSLGet<0x1B, 0x13, "neaget ", int_mblaze_fsl_neaget>;
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def NECGET : FSLGet<0x1B, 0x19, "necget ", int_mblaze_fsl_necget>;
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def NECAGET : FSLGet<0x1B, 0x1B, "necaget ", int_mblaze_fsl_necaget>;
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def TGET : FSLGet<0x1B, 0x04, "tget ", int_mblaze_fsl_tget>;
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def TAGET : FSLGet<0x1B, 0x06, "taget ", int_mblaze_fsl_taget>;
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def TCGET : FSLGet<0x1B, 0x0C, "tcget ", int_mblaze_fsl_tcget>;
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def TCAGET : FSLGet<0x1B, 0x0E, "tcaget ", int_mblaze_fsl_tcaget>;
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def TEGET : FSLGet<0x1B, 0x05, "teget ", int_mblaze_fsl_teget>;
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def TEAGET : FSLGet<0x1B, 0x07, "teaget ", int_mblaze_fsl_teaget>;
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def TECGET : FSLGet<0x1B, 0x0D, "tecget ", int_mblaze_fsl_tecget>;
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def TECAGET : FSLGet<0x1B, 0x0F, "tecaget ", int_mblaze_fsl_tecaget>;
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def TNGET : FSLGet<0x1B, 0x14, "tnget ", int_mblaze_fsl_tnget>;
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def TNAGET : FSLGet<0x1B, 0x16, "tnaget ", int_mblaze_fsl_tnaget>;
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def TNCGET : FSLGet<0x1B, 0x1C, "tncget ", int_mblaze_fsl_tncget>;
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def TNCAGET : FSLGet<0x1B, 0x1E, "tncaget ", int_mblaze_fsl_tncaget>;
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def TNEGET : FSLGet<0x1B, 0x15, "tneget ", int_mblaze_fsl_tneget>;
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def TNEAGET : FSLGet<0x1B, 0x17, "tneaget ", int_mblaze_fsl_tneaget>;
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def TNECGET : FSLGet<0x1B, 0x1D, "tnecget ", int_mblaze_fsl_tnecget>;
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def TNECAGET : FSLGet<0x1B, 0x1F, "tnecaget ", int_mblaze_fsl_tnecaget>;
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//===----------------------------------------------------------------------===//
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// FSL Dynamic Get Instructions
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//===----------------------------------------------------------------------===//
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def GETD : FSLGetD<0x13, 0x00, "getd ", int_mblaze_fsl_get>;
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def AGETD : FSLGetD<0x13, 0x02, "agetd ", int_mblaze_fsl_aget>;
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def CGETD : FSLGetD<0x13, 0x08, "cgetd ", int_mblaze_fsl_cget>;
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def CAGETD : FSLGetD<0x13, 0x0A, "cagetd ", int_mblaze_fsl_caget>;
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def EGETD : FSLGetD<0x13, 0x01, "egetd ", int_mblaze_fsl_eget>;
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def EAGETD : FSLGetD<0x13, 0x03, "eagetd ", int_mblaze_fsl_eaget>;
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def ECGETD : FSLGetD<0x13, 0x09, "ecgetd ", int_mblaze_fsl_ecget>;
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def ECAGETD : FSLGetD<0x13, 0x0B, "ecagetd ", int_mblaze_fsl_ecaget>;
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def NGETD : FSLGetD<0x13, 0x10, "ngetd ", int_mblaze_fsl_nget>;
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def NAGETD : FSLGetD<0x13, 0x12, "nagetd ", int_mblaze_fsl_naget>;
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def NCGETD : FSLGetD<0x13, 0x18, "ncgetd ", int_mblaze_fsl_ncget>;
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def NCAGETD : FSLGetD<0x13, 0x1A, "ncagetd ", int_mblaze_fsl_ncaget>;
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def NEGETD : FSLGetD<0x13, 0x11, "negetd ", int_mblaze_fsl_neget>;
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def NEAGETD : FSLGetD<0x13, 0x13, "neagetd ", int_mblaze_fsl_neaget>;
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def NECGETD : FSLGetD<0x13, 0x19, "necgetd ", int_mblaze_fsl_necget>;
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def NECAGETD : FSLGetD<0x13, 0x1B, "necagetd ", int_mblaze_fsl_necaget>;
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def TGETD : FSLGetD<0x13, 0x04, "tgetd ", int_mblaze_fsl_tget>;
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def TAGETD : FSLGetD<0x13, 0x06, "tagetd ", int_mblaze_fsl_taget>;
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def TCGETD : FSLGetD<0x13, 0x0C, "tcgetd ", int_mblaze_fsl_tcget>;
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def TCAGETD : FSLGetD<0x13, 0x0E, "tcagetd ", int_mblaze_fsl_tcaget>;
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def TEGETD : FSLGetD<0x13, 0x05, "tegetd ", int_mblaze_fsl_teget>;
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def TEAGETD : FSLGetD<0x13, 0x07, "teagetd ", int_mblaze_fsl_teaget>;
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def TECGETD : FSLGetD<0x13, 0x0D, "tecgetd ", int_mblaze_fsl_tecget>;
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def TECAGETD : FSLGetD<0x13, 0x0F, "tecagetd ", int_mblaze_fsl_tecaget>;
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def TNGETD : FSLGetD<0x13, 0x14, "tngetd ", int_mblaze_fsl_tnget>;
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def TNAGETD : FSLGetD<0x13, 0x16, "tnagetd ", int_mblaze_fsl_tnaget>;
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def TNCGETD : FSLGetD<0x13, 0x1C, "tncgetd ", int_mblaze_fsl_tncget>;
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def TNCAGETD : FSLGetD<0x13, 0x1E, "tncagetd ", int_mblaze_fsl_tncaget>;
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def TNEGETD : FSLGetD<0x13, 0x15, "tnegetd ", int_mblaze_fsl_tneget>;
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def TNEAGETD : FSLGetD<0x13, 0x17, "tneagetd ", int_mblaze_fsl_tneaget>;
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def TNECGETD : FSLGetD<0x13, 0x1D, "tnecgetd ", int_mblaze_fsl_tnecget>;
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def TNECAGETD : FSLGetD<0x13, 0x1F, "tnecagetd", int_mblaze_fsl_tnecaget>;
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//===----------------------------------------------------------------------===//
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// FSL Put Instructions
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//===----------------------------------------------------------------------===//
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def PUT : FSLPut<0x1B, 0x0, "put ", int_mblaze_fsl_put>;
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def APUT : FSLPut<0x1B, 0x1, "aput ", int_mblaze_fsl_aput>;
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def CPUT : FSLPut<0x1B, 0x4, "cput ", int_mblaze_fsl_cput>;
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def CAPUT : FSLPut<0x1B, 0x5, "caput ", int_mblaze_fsl_caput>;
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def NPUT : FSLPut<0x1B, 0x8, "nput ", int_mblaze_fsl_nput>;
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def NAPUT : FSLPut<0x1B, 0x9, "naput ", int_mblaze_fsl_naput>;
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def NCPUT : FSLPut<0x1B, 0xC, "ncput ", int_mblaze_fsl_ncput>;
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def NCAPUT : FSLPut<0x1B, 0xD, "ncaput ", int_mblaze_fsl_ncaput>;
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def TPUT : FSLPutT<0x1B, 0x2, "tput ", int_mblaze_fsl_tput>;
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def TAPUT : FSLPutT<0x1B, 0x3, "taput ", int_mblaze_fsl_taput>;
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def TCPUT : FSLPutT<0x1B, 0x6, "tcput ", int_mblaze_fsl_tcput>;
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def TCAPUT : FSLPutT<0x1B, 0x7, "tcaput ", int_mblaze_fsl_tcaput>;
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def TNPUT : FSLPutT<0x1B, 0xA, "tnput ", int_mblaze_fsl_tnput>;
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def TNAPUT : FSLPutT<0x1B, 0xB, "tnaput ", int_mblaze_fsl_tnaput>;
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def TNCPUT : FSLPutT<0x1B, 0xE, "tncput ", int_mblaze_fsl_tncput>;
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def TNCAPUT : FSLPutT<0x1B, 0xF, "tncaput ", int_mblaze_fsl_tncaput>;
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//===----------------------------------------------------------------------===//
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// FSL Dynamic Put Instructions
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//===----------------------------------------------------------------------===//
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def PUTD : FSLPutD<0x13, 0x0, "putd ", int_mblaze_fsl_put>;
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def APUTD : FSLPutD<0x13, 0x1, "aputd ", int_mblaze_fsl_aput>;
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def CPUTD : FSLPutD<0x13, 0x4, "cputd ", int_mblaze_fsl_cput>;
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def CAPUTD : FSLPutD<0x13, 0x5, "caputd ", int_mblaze_fsl_caput>;
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def NPUTD : FSLPutD<0x13, 0x8, "nputd ", int_mblaze_fsl_nput>;
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def NAPUTD : FSLPutD<0x13, 0x9, "naputd ", int_mblaze_fsl_naput>;
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def NCPUTD : FSLPutD<0x13, 0xC, "ncputd ", int_mblaze_fsl_ncput>;
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def NCAPUTD : FSLPutD<0x13, 0xD, "ncaputd ", int_mblaze_fsl_ncaput>;
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def TPUTD : FSLPutTD<0x13, 0x2, "tputd ", int_mblaze_fsl_tput>;
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def TAPUTD : FSLPutTD<0x13, 0x3, "taputd ", int_mblaze_fsl_taput>;
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def TCPUTD : FSLPutTD<0x13, 0x6, "tcputd ", int_mblaze_fsl_tcput>;
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def TCAPUTD : FSLPutTD<0x13, 0x7, "tcaputd ", int_mblaze_fsl_tcaput>;
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def TNPUTD : FSLPutTD<0x13, 0xA, "tnputd ", int_mblaze_fsl_tnput>;
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def TNAPUTD : FSLPutTD<0x13, 0xB, "tnaputd ", int_mblaze_fsl_tnaput>;
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def TNCPUTD : FSLPutTD<0x13, 0xE, "tncputd ", int_mblaze_fsl_tncput>;
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def TNCAPUTD : FSLPutTD<0x13, 0xF, "tncaputd ", int_mblaze_fsl_tncaput>;
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