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https://github.com/c64scene-ar/llvm-6502.git
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b619dd5d5b
In particular: movsbw %al, %ax --> cbtw movswl %ax, %eax --> cwtl movslq %eax, %rax --> cltq According to Intel's manual those have the same performance characteristics but come with a smaller encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186174 91177308-0d34-0410-b5e6-96231b3b80d8
39 lines
899 B
LLVM
39 lines
899 B
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -mtriple i686-apple-darwin10 | FileCheck %s
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; RUN: llc < %s -O0 -fast-isel-abort -mtriple x86_64-apple-darwin10 | FileCheck %s
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define zeroext i8 @test1(i32 %y) nounwind {
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%conv = trunc i32 %y to i8
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ret i8 %conv
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; CHECK: test1:
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; CHECK: movzbl {{.*}}, %eax
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}
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define signext i8 @test2(i32 %y) nounwind {
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%conv = trunc i32 %y to i8
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ret i8 %conv
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; CHECK: test2:
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; CHECK: movsbl {{.*}}, %eax
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}
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define zeroext i16 @test3(i32 %y) nounwind {
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%conv = trunc i32 %y to i16
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ret i16 %conv
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; CHECK: test3:
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; CHECK: movzwl {{.*}}, %eax
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}
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define signext i16 @test4(i32 %y) nounwind {
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%conv = trunc i32 %y to i16
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ret i16 %conv
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; CHECK: test4:
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; CHECK: {{(movswl.%.x, %eax|cwtl)}}
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}
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define zeroext i1 @test5(i32 %y) nounwind {
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%conv = trunc i32 %y to i1
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ret i1 %conv
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; CHECK: test5:
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; CHECK: andb $1
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; CHECK: movzbl {{.*}}, %eax
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}
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