6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-10 18:26:02 +00:00
Code Issues Projects Releases Wiki Activity
Files
7740daa8ba053294b7448556c049cf6778711d66
llvm-6502/lib/Target/R600
History
Michel Danzer 7740daa8ba R600/SI: Initial support for LDS/GDS instructions 
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186009 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-10 16:36:43 +00:00
..
InstPrinter
R600: Bank Swizzle now display SCL equivalent
2013-06-29 19:32:29 +00:00
MCTargetDesc
Remove address spaces from MC.
2013-07-02 15:49:13 +00:00
TargetInfo
…
AMDGPU.h
…
AMDGPU.td
R600: Rework subtarget info and remove AMDILDevice classes
2013-06-07 20:37:48 +00:00
AMDGPUAsmPrinter.cpp
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
AMDGPUAsmPrinter.h
…
AMDGPUCallingConv.td
…
AMDGPUConvertToISA.cpp
…
AMDGPUFrameLowering.cpp
R600: Fix calculation of stack offset in AMDGPUFrameLowering
2013-06-07 20:52:05 +00:00
AMDGPUFrameLowering.h
R600: Support for indirect addressing v4
2013-02-06 17:32:29 +00:00
AMDGPUIndirectAddressing.cpp
…
AMDGPUInstrInfo.cpp
…
AMDGPUInstrInfo.h
R600: Use new getNamedOperandIdx function generated by TableGen
2013-06-25 21:22:18 +00:00
AMDGPUInstrInfo.td
…
AMDGPUInstructions.td
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
AMDGPUIntrinsics.td
…
AMDGPUISelLowering.cpp
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
AMDGPUISelLowering.h
R600: Use DAG lowering pass to handle fcos/fsin
2013-07-09 15:03:11 +00:00
AMDGPUMachineFunction.cpp
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
AMDGPUMachineFunction.h
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
AMDGPUMCInstLower.cpp
…
AMDGPUMCInstLower.h
…
AMDGPURegisterInfo.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
AMDGPURegisterInfo.h
…
AMDGPURegisterInfo.td
Make SubRegIndex size mandatory, following r183020.
2013-05-31 23:45:26 +00:00
AMDGPUSubtarget.cpp
…
AMDGPUSubtarget.h
…
AMDGPUTargetMachine.cpp
R600: Do not predicated basic block with multiple alu clause
2013-07-09 15:03:33 +00:00
AMDGPUTargetMachine.h
…
AMDILBase.td
…
AMDILCFGStructurizer.cpp
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
2013-07-03 15:07:05 +00:00
AMDILInstrInfo.td
…
AMDILIntrinsicInfo.cpp
…
AMDILIntrinsicInfo.h
…
AMDILIntrinsics.td
R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern
2013-02-18 14:11:28 +00:00
AMDILISelDAGToDAG.cpp
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
AMDILISelLowering.cpp
…
AMDILRegisterInfo.td
Add R600 backend
2012-12-11 21:25:42 +00:00
CMakeLists.txt
…
LLVMBuild.txt
Add R600 backend
2012-12-11 21:25:42 +00:00
Makefile
…
Processors.td
Add a newline.
2013-07-01 21:31:10 +00:00
R600ControlFlowFinalizer.cpp
R600: Do not predicated basic block with multiple alu clause
2013-07-09 15:03:33 +00:00
R600Defines.h
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
R600EmitClauseMarkers.cpp
R600: Do not predicated basic block with multiple alu clause
2013-07-09 15:03:33 +00:00
R600ExpandSpecialInstrs.cpp
…
R600InstrFormats.td
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
R600InstrInfo.cpp
R600: Do not predicated basic block with multiple alu clause
2013-07-09 15:03:33 +00:00
R600InstrInfo.h
R600: Support schedule and packetization of trans-only inst
2013-06-29 19:32:43 +00:00
R600Instructions.td
R600: Do not predicated basic block with multiple alu clause
2013-07-09 15:03:33 +00:00
R600Intrinsics.td
…
R600ISelLowering.cpp
R600: Fix a rare bug where swizzle optimization returns wrong values
2013-07-09 15:03:25 +00:00
R600ISelLowering.h
R600: Use DAG lowering pass to handle fcos/fsin
2013-07-09 15:03:11 +00:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
R600: Support schedule and packetization of trans-only inst
2013-06-29 19:32:43 +00:00
R600MachineScheduler.h
R600: Support schedule and packetization of trans-only inst
2013-06-29 19:32:43 +00:00
R600OptimizeVectorRegisters.cpp
R600: Fix wrong export reswizzling
2013-07-09 15:03:19 +00:00
R600Packetizer.cpp
R600: Do not predicated basic block with multiple alu clause
2013-07-09 15:03:33 +00:00
R600RegisterInfo.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
R600RegisterInfo.h
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
R600RegisterInfo.td
R600: Support schedule and packetization of trans-only inst
2013-06-29 19:32:43 +00:00
R600Schedule.td
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
R600TextureIntrinsicsReplacer.cpp
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
2013-05-23 17:10:37 +00:00
SIAnnotateControlFlow.cpp
…
SIDefines.h
…
SIInsertWaits.cpp
R600/SI: Initial support for LDS/GDS instructions
2013-07-10 16:36:43 +00:00
SIInstrFormats.td
R600/SI: Initial support for LDS/GDS instructions
2013-07-10 16:36:43 +00:00
SIInstrInfo.cpp
…
SIInstrInfo.h
R600/SI: adjust writemask to only the used components
2013-04-10 08:39:08 +00:00
SIInstrInfo.td
R600/SI: Initial support for LDS/GDS instructions
2013-07-10 16:36:43 +00:00
SIInstructions.td
R600/SI: Initial support for LDS/GDS instructions
2013-07-10 16:36:43 +00:00
SIIntrinsics.td
R600/SI: Add intrinsics for texture sampling with user derivatives
2013-07-10 16:36:36 +00:00
SIISelLowering.cpp
R600: Consolidate expansion of v2i32/v4i32 ops for EG/SI
2013-06-25 13:55:57 +00:00
SIISelLowering.h
…
SILowerControlFlow.cpp
R600/SI: Initial support for LDS/GDS instructions
2013-07-10 16:36:43 +00:00
SIMachineFunctionInfo.cpp
R600/SI: Share code recording ShaderTypeAttribute between generations
2013-04-01 21:47:53 +00:00
SIMachineFunctionInfo.h
…
SIRegisterInfo.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
SIRegisterInfo.h
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
SIRegisterInfo.td
R600/SI: dynamical figure out the reg class of MIMG
2013-04-10 08:39:16 +00:00
SISchedule.td
…