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https://github.com/c64scene-ar/llvm-6502.git
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a8e2989ece
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
119 lines
4.2 KiB
C++
119 lines
4.2 KiB
C++
//===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the "Instituto Nokia de Tecnologia" and
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// is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "../Target.td"
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//===----------------------------------------------------------------------===//
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// ARM Subtarget features.
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//
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def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
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"ARM v4T">;
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def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
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"ARM v5T">;
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def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
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"ARM v5TE, v5TEj, v5TExp">;
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def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6",
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"ARM v6">;
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def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFP2", "true",
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"Enable VFP2 instructions ">;
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//===----------------------------------------------------------------------===//
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// ARM Processors supported.
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//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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// V4 Processors.
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def : Proc<"generic", []>;
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def : Proc<"arm8", []>;
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def : Proc<"arm810", []>;
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def : Proc<"strongarm", []>;
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def : Proc<"strongarm110", []>;
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def : Proc<"strongarm1100", []>;
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def : Proc<"strongarm1110", []>;
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// V4T Processors.
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def : Proc<"arm7tdmi", [ArchV4T]>;
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def : Proc<"arm7tdmi-s", [ArchV4T]>;
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def : Proc<"arm710t", [ArchV4T]>;
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def : Proc<"arm720t", [ArchV4T]>;
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def : Proc<"arm9", [ArchV4T]>;
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def : Proc<"arm9tdmi", [ArchV4T]>;
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def : Proc<"arm920", [ArchV4T]>;
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def : Proc<"arm920t", [ArchV4T]>;
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def : Proc<"arm922t", [ArchV4T]>;
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def : Proc<"arm940t", [ArchV4T]>;
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def : Proc<"ep9312", [ArchV4T]>;
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// V5T Processors.
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def : Proc<"arm10tdmi", [ArchV5T]>;
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def : Proc<"arm1020t", [ArchV5T]>;
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// V5TE Processors.
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def : Proc<"arm9e", [ArchV5TE]>;
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def : Proc<"arm946e-s", [ArchV5TE]>;
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def : Proc<"arm966e-s", [ArchV5TE]>;
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def : Proc<"arm968e-s", [ArchV5TE]>;
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def : Proc<"arm10e", [ArchV5TE]>;
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def : Proc<"arm1020e", [ArchV5TE]>;
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def : Proc<"arm1022e", [ArchV5TE]>;
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def : Proc<"xscale", [ArchV5TE]>;
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def : Proc<"iwmmxt", [ArchV5TE]>;
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// V6 Processors.
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def : Proc<"arm1136j-s", [ArchV6]>;
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def : Proc<"arm1136jf-s", [ArchV6, FeatureVFP2]>;
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def : Proc<"arm1176jz-s", [ArchV6]>;
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def : Proc<"arm1176jzf-s", [ArchV6, FeatureVFP2]>;
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def : Proc<"mpcorenovfp", [ArchV6]>;
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def : Proc<"mpcore", [ArchV6, FeatureVFP2]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "ARMRegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "ARMInstrInfo.td"
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def ARMInstrInfo : InstrInfo {
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// Define how we want to layout our target-specific information field.
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let TSFlagsFields = ["AddrModeBits",
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"SizeFlag",
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"IndexModeBits",
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"Opcode"];
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let TSFlagsShifts = [0,
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4,
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7,
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9];
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}
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def ARM : Target {
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// Pull in Instruction Info:
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let InstructionSet = ARMInstrInfo;
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}
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