mirror of
https://github.com/c64scene-ar/llvm-6502.git
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a8e2989ece
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
360 lines
12 KiB
TableGen
360 lines
12 KiB
TableGen
//===- ARMInstrVFP.td - VFP support for ARM -------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the ARM VP instruction set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ARM VFP Instruction templates.
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//
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// ARM Float Instruction
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class ASI<dag ops, string asm, list<dag> pattern> : AI<ops, asm, pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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class ASI5<dag ops, string asm, list<dag> pattern>
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: I<ops, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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// ARM Double Instruction
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class ADI<dag ops, string asm, list<dag> pattern> : AI<ops, asm, pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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class ADI5<dag ops, string asm, list<dag> pattern>
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: I<ops, AddrMode5, Size4Bytes, IndexModeNone, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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}
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def SDT_FTOI :
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SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
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def SDT_ITOF :
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
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def SDT_CMPFP0 :
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SDTypeProfile<0, 1, [SDTCisFP<0>]>;
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def SDT_FMDRR :
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SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
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SDTCisSameAs<1, 2>]>;
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def arm_ftoui : SDNode<"ARMISD::FTOUI", SDT_FTOI>;
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def arm_ftosi : SDNode<"ARMISD::FTOSI", SDT_FTOI>;
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def arm_sitof : SDNode<"ARMISD::SITOF", SDT_ITOF>;
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def arm_uitof : SDNode<"ARMISD::UITOF", SDT_ITOF>;
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def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTRet, [SDNPInFlag,SDNPOutFlag]>;
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def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutFlag]>;
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def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutFlag]>;
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def arm_fmdrr : SDNode<"ARMISD::FMDRR", SDT_FMDRR>;
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//===----------------------------------------------------------------------===//
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// Load / store Instructions.
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//
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let isLoad = 1 in {
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def FLDD : ADI5<(ops DPR:$dst, addrmode5:$addr),
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"fldd $dst, $addr",
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[(set DPR:$dst, (load addrmode5:$addr))]>;
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def FLDS : ASI5<(ops SPR:$dst, addrmode5:$addr),
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"flds $dst, $addr",
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[(set SPR:$dst, (load addrmode5:$addr))]>;
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} // isLoad
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let isStore = 1 in {
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def FSTD : ADI5<(ops DPR:$src, addrmode5:$addr),
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"fstd $src, $addr",
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[(store DPR:$src, addrmode5:$addr)]>;
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def FSTS : ASI5<(ops SPR:$src, addrmode5:$addr),
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"fsts $src, $addr",
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[(store SPR:$src, addrmode5:$addr)]>;
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} // isStore
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//===----------------------------------------------------------------------===//
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// Load / store multiple Instructions.
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//
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let isLoad = 1 in {
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def FLDMD : ADI5<(ops addrmode5:$addr, reglist:$dst1, variable_ops),
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"fldm${addr:submode}d ${addr:base}, $dst1",
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[]>;
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def FLDMS : ASI5<(ops addrmode5:$addr, reglist:$dst1, variable_ops),
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"fldm${addr:submode}s ${addr:base}, $dst1",
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[]>;
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} // isLoad
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let isStore = 1 in {
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def FSTMD : ADI5<(ops addrmode5:$addr, reglist:$src1, variable_ops),
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"fstm${addr:submode}d ${addr:base}, $src1",
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[]>;
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def FSTMS : ASI5<(ops addrmode5:$addr, reglist:$src1, variable_ops),
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"fstm${addr:submode}s ${addr:base}, $src1",
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[]>;
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} // isStore
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// FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
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//===----------------------------------------------------------------------===//
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// FP Binary Operations.
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//
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def FADDD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
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"faddd $dst, $a, $b",
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[(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
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def FADDS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
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"fadds $dst, $a, $b",
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[(set SPR:$dst, (fadd SPR:$a, SPR:$b))]>;
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def FCMPED : ADI<(ops DPR:$a, DPR:$b),
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"fcmped $a, $b",
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[(arm_cmpfp DPR:$a, DPR:$b)]>;
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def FCMPES : ASI<(ops SPR:$a, SPR:$b),
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"fcmpes $a, $b",
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[(arm_cmpfp SPR:$a, SPR:$b)]>;
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def FDIVD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
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"fdivd $dst, $a, $b",
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[(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
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def FDIVS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
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"fdivs $dst, $a, $b",
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[(set SPR:$dst, (fdiv SPR:$a, SPR:$b))]>;
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def FMULD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
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"fmuld $dst, $a, $b",
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[(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
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def FMULS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
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"fmuls $dst, $a, $b",
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[(set SPR:$dst, (fmul SPR:$a, SPR:$b))]>;
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def FNMULD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
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"fnmuld $dst, $a, $b",
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[(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]>;
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def FNMULS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
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"fnmuls $dst, $a, $b",
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[(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]>;
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def FSUBD : ADI<(ops DPR:$dst, DPR:$a, DPR:$b),
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"fsubd $dst, $a, $b",
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[(set DPR:$dst, (fsub DPR:$a, DPR:$b))]>;
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def FSUBS : ASI<(ops SPR:$dst, SPR:$a, SPR:$b),
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"fsubs $dst, $a, $b",
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[(set SPR:$dst, (fsub SPR:$a, SPR:$b))]>;
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//===----------------------------------------------------------------------===//
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// FP Unary Operations.
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//
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def FABSD : ADI<(ops DPR:$dst, DPR:$a),
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"fabsd $dst, $a",
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[(set DPR:$dst, (fabs DPR:$a))]>;
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def FABSS : ASI<(ops SPR:$dst, SPR:$a),
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"fabss $dst, $a",
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[(set SPR:$dst, (fabs SPR:$a))]>;
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def FCMPEZD : ADI<(ops DPR:$a),
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"fcmpezd $a",
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[(arm_cmpfp0 DPR:$a)]>;
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def FCMPEZS : ASI<(ops SPR:$a),
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"fcmpezs $a",
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[(arm_cmpfp0 SPR:$a)]>;
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def FCVTDS : ADI<(ops DPR:$dst, SPR:$a),
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"fcvtds $dst, $a",
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[(set DPR:$dst, (fextend SPR:$a))]>;
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def FCVTSD : ADI<(ops SPR:$dst, DPR:$a),
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"fcvtsd $dst, $a",
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[(set SPR:$dst, (fround DPR:$a))]>;
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def FCPYD : ADI<(ops DPR:$dst, DPR:$a),
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"fcpyd $dst, $a",
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[/*(set DPR:$dst, DPR:$a)*/]>;
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def FCPYS : ASI<(ops SPR:$dst, SPR:$a),
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"fcpys $dst, $a",
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[/*(set SPR:$dst, SPR:$a)*/]>;
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def FNEGD : ADI<(ops DPR:$dst, DPR:$a),
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"fnegd $dst, $a",
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[(set DPR:$dst, (fneg DPR:$a))]>;
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def FNEGS : ASI<(ops SPR:$dst, SPR:$a),
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"fnegs $dst, $a",
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[(set SPR:$dst, (fneg SPR:$a))]>;
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def FSQRTD : ADI<(ops DPR:$dst, DPR:$a),
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"fsqrtd $dst, $a",
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[(set DPR:$dst, (fsqrt DPR:$a))]>;
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def FSQRTS : ASI<(ops SPR:$dst, SPR:$a),
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"fsqrts $dst, $a",
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[(set SPR:$dst, (fsqrt SPR:$a))]>;
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//===----------------------------------------------------------------------===//
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// FP <-> GPR Copies. Int <-> FP Conversions.
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//
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def IMPLICIT_DEF_SPR : PseudoInst<(ops SPR:$rD),
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"@ IMPLICIT_DEF_SPR $rD",
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[(set SPR:$rD, (undef))]>;
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def IMPLICIT_DEF_DPR : PseudoInst<(ops DPR:$rD),
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"@ IMPLICIT_DEF_DPR $rD",
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[(set DPR:$rD, (undef))]>;
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def FMRS : ASI<(ops GPR:$dst, SPR:$src),
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"fmrs $dst, $src",
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[(set GPR:$dst, (bitconvert SPR:$src))]>;
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def FMSR : ASI<(ops SPR:$dst, GPR:$src),
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"fmsr $dst, $src",
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[(set SPR:$dst, (bitconvert GPR:$src))]>;
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def FMRRD : ADI<(ops GPR:$dst1, GPR:$dst2, DPR:$src),
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"fmrrd $dst1, $dst2, $src",
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[/* FIXME: Can't write pattern for multiple result instr*/]>;
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// FMDHR: GPR -> SPR
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// FMDLR: GPR -> SPR
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def FMDRR : ADI<(ops DPR:$dst, GPR:$src1, GPR:$src2),
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"fmdrr $dst, $src1, $src2",
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[(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]>;
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// FMRDH: SPR -> GPR
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// FMRDL: SPR -> GPR
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// FMRRS: SPR -> GPR
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// FMRX : SPR system reg -> GPR
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// FMSRR: GPR -> SPR
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def FMSTAT : ASI<(ops), "fmstat", [(arm_fmstat)]>;
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// FMXR: GPR -> VFP Sstem reg
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// Int to FP:
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def FSITOD : ADI<(ops DPR:$dst, SPR:$a),
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"fsitod $dst, $a",
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[(set DPR:$dst, (arm_sitof SPR:$a))]>;
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def FSITOS : ASI<(ops SPR:$dst, SPR:$a),
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"fsitos $dst, $a",
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[(set SPR:$dst, (arm_sitof SPR:$a))]>;
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def FUITOD : ADI<(ops DPR:$dst, SPR:$a),
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"fuitod $dst, $a",
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[(set DPR:$dst, (arm_uitof SPR:$a))]>;
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def FUITOS : ASI<(ops SPR:$dst, SPR:$a),
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"fuitos $dst, $a",
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[(set SPR:$dst, (arm_uitof SPR:$a))]>;
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// FP to Int:
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// Always set Z bit in the instruction, i.e. "round towards zero" variants.
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def FTOSIZD : ADI<(ops SPR:$dst, DPR:$a),
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"ftosizd $dst, $a",
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[(set SPR:$dst, (arm_ftosi DPR:$a))]>;
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def FTOSIZS : ASI<(ops SPR:$dst, SPR:$a),
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"ftosizs $dst, $a",
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[(set SPR:$dst, (arm_ftosi SPR:$a))]>;
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def FTOUIZD : ADI<(ops SPR:$dst, DPR:$a),
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"ftouizd $dst, $a",
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[(set SPR:$dst, (arm_ftoui DPR:$a))]>;
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def FTOUIZS : ASI<(ops SPR:$dst, SPR:$a),
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"ftouizs $dst, $a",
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[(set SPR:$dst, (arm_ftoui SPR:$a))]>;
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//===----------------------------------------------------------------------===//
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// FP FMA Operations.
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//
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def FMACD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
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"fmacd $dst, $a, $b",
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[(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def FMACS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
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"fmacs $dst, $a, $b",
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[(set SPR:$dst, (fadd (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def FMSCD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
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"fmscd $dst, $a, $b",
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[(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def FMSCS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
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"fmscs $dst, $a, $b",
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[(set SPR:$dst, (fsub (fmul SPR:$a, SPR:$b), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def FNMACD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
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"fnmacd $dst, $a, $b",
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[(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def FNMACS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
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"fnmacs $dst, $a, $b",
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[(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def FNMSCD : ADI<(ops DPR:$dst, DPR:$dstin, DPR:$a, DPR:$b),
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"fnmscd $dst, $a, $b",
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[(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def FNMSCS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
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"fnmscs $dst, $a, $b",
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[(set SPR:$dst, (fsub (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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//===----------------------------------------------------------------------===//
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// FP Conditional moves.
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//
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def FCPYDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, CCOp:$cc),
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"fcpyd$cc $dst, $true",
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[(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))]>,
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RegConstraint<"$false = $dst">;
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def FCPYScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, CCOp:$cc),
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"fcpys$cc $dst, $true",
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[(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))]>,
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RegConstraint<"$false = $dst">;
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def FNEGDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, CCOp:$cc),
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"fnegd$cc $dst, $true",
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[(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))]>,
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RegConstraint<"$false = $dst">;
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def FNEGScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, CCOp:$cc),
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"fnegs$cc $dst, $true",
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[(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))]>,
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RegConstraint<"$false = $dst">;
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