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https://github.com/c64scene-ar/llvm-6502.git
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b451f4e376
Thumb-1 only allows SP-based LDR and STR to be word-sized, and SP-base LDR, STR, and ADD only allow offsets that are a multiple of 4. Make some changes to better make use of these instructions: * Use word loads for anyext byte and halfword loads from the stack. * Enforce 4-byte alignment on objects accessed in this way, to ensure that the offset is valid. * Do the same for objects whose frame index is used, in order to avoid having to use more than one ADD to generate the frame index. * Correct how many bits of offset we think AddrModeT1_s has. Patch by John Brawn. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230496 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
1.7 KiB
LLVM
75 lines
1.7 KiB
LLVM
; RUN: llc -mtriple=thumb-eabi < %s -o - | FileCheck %s
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; Check that stack addresses are generated using a single ADD
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define void @test1(i8** %p) {
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%x = alloca i8, align 1
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%y = alloca i8, align 1
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%z = alloca i8, align 1
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; CHECK: add r1, sp, #8
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; CHECK: str r1, [r0]
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store i8* %x, i8** %p, align 4
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; CHECK: add r1, sp, #4
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; CHECK: str r1, [r0]
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store i8* %y, i8** %p, align 4
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; CHECK: mov r1, sp
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; CHECK: str r1, [r0]
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store i8* %z, i8** %p, align 4
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ret void
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}
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; Stack offsets larger than 1020 still need two ADDs
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define void @test2([1024 x i8]** %p) {
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%arr1 = alloca [1024 x i8], align 1
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%arr2 = alloca [1024 x i8], align 1
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; CHECK: add r1, sp, #1020
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; CHECK: adds r1, #4
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; CHECK: str r1, [r0]
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store [1024 x i8]* %arr1, [1024 x i8]** %p, align 4
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; CHECK: mov r1, sp
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; CHECK: str r1, [r0]
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store [1024 x i8]* %arr2, [1024 x i8]** %p, align 4
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ret void
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}
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; If possible stack-based lrdb/ldrh are widened to use SP-based addressing
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define i32 @test3() #0 {
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%x = alloca i8, align 1
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%y = alloca i8, align 1
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; CHECK: ldr r0, [sp]
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%1 = load i8* %x, align 1
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; CHECK: ldr r1, [sp, #4]
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%2 = load i8* %y, align 1
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%3 = add nsw i8 %1, %2
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%4 = zext i8 %3 to i32
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ret i32 %4
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}
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define i32 @test4() #0 {
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%x = alloca i16, align 2
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%y = alloca i16, align 2
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; CHECK: ldr r0, [sp]
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%1 = load i16* %x, align 2
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; CHECK: ldr r1, [sp, #4]
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%2 = load i16* %y, align 2
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%3 = add nsw i16 %1, %2
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%4 = zext i16 %3 to i32
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ret i32 %4
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}
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; Don't widen if the value needs to be zero-extended
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define zeroext i8 @test5() {
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%x = alloca i8, align 1
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; CHECK: mov r0, sp
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; CHECK: ldrb r0, [r0]
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%1 = load i8* %x, align 1
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ret i8 %1
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}
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define zeroext i16 @test6() {
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%x = alloca i16, align 2
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; CHECK: mov r0, sp
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; CHECK: ldrh r0, [r0]
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%1 = load i16* %x, align 2
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ret i16 %1
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}
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