Vikram S. Adve 78a4f23a8e Added special register class containing (for now) %fsr. ...

Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6339 91177308-0d34-0410-b5e6-96231b3b80d8

2003-05-27 00:02:22 +00:00

..

CBackend

Add support for setjmp/longjmp primitives

2003-05-17 22:26:33 +00:00

SparcV9

Added special register class containing (for now) %fsr.

2003-05-27 00:02:22 +00:00

X86

Reword to remove reference to how things worked in the past.

2003-05-24 01:08:43 +00:00

Makefile

X86 target builds fine now

2002-11-20 20:17:03 +00:00

MRegisterInfo.cpp

Capture more information in ctor

2002-12-28 20:34:18 +00:00

TargetData.cpp

* Fix divide by zero error with empty structs

2003-05-21 18:08:44 +00:00

TargetInstrInfo.cpp

Rename MachineInstrInfo -> TargetInstrInfo

2003-01-14 22:00:31 +00:00

TargetMachine.cpp

The promotion rules are the same for all targets, they are set by the C standard.

2003-04-26 19:47:36 +00:00

TargetSchedInfo.cpp

More renamings of Target/Machine*Info to Target/Target*Info

2002-12-29 03:13:05 +00:00