Richard Sandiford 79e2ed4d83 [SystemZ] Add register zero extensions involving at least one high word ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191746 91177308-0d34-0410-b5e6-96231b3b80d8

2013-10-01 12:49:07 +00:00

..

AArch64

llvm/test/CodeGen/AArch64/neon-scalar-reduce-pairwise.ll: Use -mtriple here, or aach64-pecoff might be misassumed on win32 hosts.

2013-09-24 04:14:29 +00:00

ARM

[ARM] Introduce the 'sevl' instruction in ARMv8.

2013-10-01 12:39:11 +00:00

CPP

[tests] Cleanup initialization of test suffixes.

2013-08-16 00:37:11 +00:00

Generic

[tests] Cleanup initialization of test suffixes.

2013-08-16 00:37:11 +00:00

Hexagon

TBAA: remove !tbaa from testing cases when they are not needed.

2013-09-30 18:17:35 +00:00

Inputs

Debug Info: add an identifier field to DICompositeType.

2013-08-26 22:39:55 +00:00

Mips

[mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics)

2013-10-01 10:22:35 +00:00

MSP430

[tests] Cleanup initialization of test suffixes.

2013-08-16 00:37:11 +00:00

NVPTX

[NVPTX] Make constant vector test case endian-independent

2013-09-19 13:14:44 +00:00

PowerPC

TBAA: update tbaa format from scalar format to struct-path aware format.

2013-09-30 18:17:55 +00:00

R600

TBAA: update tbaa format from scalar format to struct-path aware format.

2013-09-30 18:17:55 +00:00

SPARC

TBAA: update tbaa format from scalar format to struct-path aware format.

2013-09-30 18:17:55 +00:00

SystemZ

[SystemZ] Add register zero extensions involving at least one high word

2013-10-01 12:49:07 +00:00

Thumb

ARM: Use "dmb sy" for barriers on M-class CPUs

2013-08-28 14:39:19 +00:00

Thumb2

Fix spelling intruction -> instruction.

2013-09-28 11:46:15 +00:00

X86

AVX-512: Added X86vzmovl patterns

2013-10-01 08:38:02 +00:00

XCore

XCore handling of thread local lowering

2013-09-09 10:42:11 +00:00