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https://github.com/c64scene-ar/llvm-6502.git
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66aefa805b
This brings MC into line with GNU 'as' on ARM, and it brings the ARM target into line with most other LLVM targets, which declare the initial CFI state with addInitialFrameState(). Without this, functions generated with .cfi_startproc/endproc on ARM will tend to cause GDB to abort with: gdb/dwarf2-frame.c:1132: internal-error: Unknown CFA rule. I've also tested this by comparing the output of "readelf -w" on the object files produced by llvm-mc and gas when given the .s file added here. This change is part of addressing PR18636. Differential Revision: http://llvm-reviews.chandlerc.com/D2597 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200255 91177308-0d34-0410-b5e6-96231b3b80d8
376 lines
13 KiB
C++
376 lines
13 KiB
C++
//===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides ARM specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMBaseInfo.h"
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#include "ARMMCAsmInfo.h"
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#include "ARMMCTargetDesc.h"
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#include "InstPrinter/ARMInstPrinter.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/MCCodeGenInfo.h"
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#include "llvm/MC/MCELFStreamer.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_REGINFO_MC_DESC
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#include "ARMGenRegisterInfo.inc"
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static bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
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std::string &Info) {
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if (STI.getFeatureBits() & llvm::ARM::HasV7Ops &&
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(MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
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(MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
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// Checks for the deprecated CP15ISB encoding:
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// mcr p15, #0, rX, c7, c5, #4
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(MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
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if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
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if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
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Info = "deprecated since v7, use 'isb'";
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return true;
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}
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// Checks for the deprecated CP15DSB encoding:
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// mcr p15, #0, rX, c7, c10, #4
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if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
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Info = "deprecated since v7, use 'dsb'";
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return true;
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}
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}
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// Checks for the deprecated CP15DMB encoding:
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// mcr p15, #0, rX, c7, c10, #5
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if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
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(MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
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Info = "deprecated since v7, use 'dmb'";
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return true;
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}
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}
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return false;
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}
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static bool getITDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
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std::string &Info) {
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if (STI.getFeatureBits() & llvm::ARM::HasV8Ops &&
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MI.getOperand(1).isImm() && MI.getOperand(1).getImm() != 8) {
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Info = "applying IT instruction to more than one subsequent instruction is deprecated";
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return true;
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}
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return false;
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}
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#define GET_INSTRINFO_MC_DESC
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#include "ARMGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "ARMGenSubtargetInfo.inc"
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std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
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Triple triple(TT);
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// Set the boolean corresponding to the current target triple, or the default
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// if one cannot be determined, to true.
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unsigned Len = TT.size();
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unsigned Idx = 0;
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// FIXME: Enhance Triple helper class to extract ARM version.
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bool isThumb = triple.getArch() == Triple::thumb;
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if (Len >= 5 && TT.substr(0, 4) == "armv")
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Idx = 4;
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else if (Len >= 7 && TT.substr(0, 6) == "thumbv")
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Idx = 6;
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bool NoCPU = CPU == "generic" || CPU.empty();
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std::string ARMArchFeature;
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if (Idx) {
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unsigned SubVer = TT[Idx];
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if (SubVer == '8') {
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if (NoCPU)
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// v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2, FeatureMP,
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// FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone, FeatureT2XtPk, FeatureCrypto, FeatureCRC
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ARMArchFeature = "+v8,+db,+fp-armv8,+neon,+t2dsp,+mp,+hwdiv,+hwdiv-arm,+trustzone,+t2xtpk,+crypto,+crc";
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else
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// Use CPU to figure out the exact features
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ARMArchFeature = "+v8";
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} else if (SubVer == '7') {
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if (Len >= Idx+2 && TT[Idx+1] == 'm') {
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isThumb = true;
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if (NoCPU)
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// v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
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ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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} else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
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if (NoCPU)
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// v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
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// FeatureT2XtPk, FeatureMClass
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ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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} else if (Len >= Idx+2 && TT[Idx+1] == 's') {
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if (NoCPU)
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// v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
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// Swift
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ARMArchFeature = "+v7,+swift,+neon,+db,+t2dsp,+ras";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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} else {
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// v7 CPUs have lots of different feature sets. If no CPU is specified,
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// then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
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// the "minimum" feature set and use CPU string to figure out the exact
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// features.
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if (NoCPU)
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// v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
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ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
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else
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// Use CPU to figure out the exact features.
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ARMArchFeature = "+v7";
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}
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} else if (SubVer == '6') {
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
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ARMArchFeature = "+v6t2";
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else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
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isThumb = true;
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if (NoCPU)
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// v6m: FeatureNoARM, FeatureMClass
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ARMArchFeature = "+v6m,+noarm,+mclass";
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else
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ARMArchFeature = "+v6";
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} else
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ARMArchFeature = "+v6";
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} else if (SubVer == '5') {
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if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
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ARMArchFeature = "+v5te";
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else
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ARMArchFeature = "+v5t";
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} else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
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ARMArchFeature = "+v4t";
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}
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if (isThumb) {
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if (ARMArchFeature.empty())
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ARMArchFeature = "+thumb-mode";
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else
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ARMArchFeature += ",+thumb-mode";
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}
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if (triple.isOSNaCl()) {
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if (ARMArchFeature.empty())
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ARMArchFeature = "+nacl-trap";
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else
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ARMArchFeature += ",+nacl-trap";
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}
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return ARMArchFeature;
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}
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MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
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StringRef FS) {
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std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
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if (!FS.empty()) {
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if (!ArchFS.empty())
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ArchFS = ArchFS + "," + FS.str();
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else
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ArchFS = FS;
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}
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MCSubtargetInfo *X = new MCSubtargetInfo();
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InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
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return X;
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}
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static MCInstrInfo *createARMMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitARMMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
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return X;
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}
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static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
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Triple TheTriple(TT);
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MCAsmInfo *MAI;
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if (TheTriple.isOSBinFormatMachO())
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MAI = new ARMMCAsmInfoDarwin();
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else
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MAI = new ARMELFMCAsmInfo();
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unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
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MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(0, Reg, 0));
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return MAI;
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}
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static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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if (RM == Reloc::Default) {
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Triple TheTriple(TT);
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// Default relocation model on Darwin is PIC, not DynamicNoPIC.
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RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
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}
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X->InitMCCodeGenInfo(RM, CM, OL);
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return X;
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}
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// This is duplicated code. Refactor this.
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static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
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MCContext &Ctx, MCAsmBackend &MAB,
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raw_ostream &OS,
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MCCodeEmitter *Emitter,
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const MCSubtargetInfo &STI,
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bool RelaxAll,
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bool NoExecStack) {
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Triple TheTriple(TT);
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if (TheTriple.isOSBinFormatMachO())
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return createMachOStreamer(Ctx, MAB, OS, Emitter, false);
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if (TheTriple.isOSWindows()) {
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llvm_unreachable("ARM does not support Windows COFF format");
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}
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return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack,
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TheTriple.getArch() == Triple::thumb);
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}
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static MCInstPrinter *createARMMCInstPrinter(const Target &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI) {
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if (SyntaxVariant == 0)
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return new ARMInstPrinter(MAI, MII, MRI, STI);
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return 0;
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}
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static MCRelocationInfo *createARMMCRelocationInfo(StringRef TT,
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MCContext &Ctx) {
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Triple TheTriple(TT);
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if (TheTriple.isOSBinFormatMachO())
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return createARMMachORelocationInfo(Ctx);
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// Default to the stock relocation info.
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return llvm::createMCRelocationInfo(TT, Ctx);
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}
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namespace {
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class ARMMCInstrAnalysis : public MCInstrAnalysis {
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public:
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ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
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virtual bool isUnconditionalBranch(const MCInst &Inst) const {
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// BCCs with the "always" predicate are unconditional branches.
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if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
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return true;
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return MCInstrAnalysis::isUnconditionalBranch(Inst);
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}
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virtual bool isConditionalBranch(const MCInst &Inst) const {
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// BCCs with the "always" predicate are unconditional branches.
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if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
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return false;
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return MCInstrAnalysis::isConditionalBranch(Inst);
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}
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bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
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uint64_t Size, uint64_t &Target) const {
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// We only handle PCRel branches for now.
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if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
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return false;
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int64_t Imm = Inst.getOperand(0).getImm();
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// FIXME: This is not right for thumb.
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Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
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return true;
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}
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};
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}
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static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
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return new ARMMCInstrAnalysis(Info);
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}
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// Force static initialization.
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extern "C" void LLVMInitializeARMTargetMC() {
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// Register the MC asm info.
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RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
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RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
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// Register the MC codegen info.
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TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
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TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
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TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
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TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
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ARM_MC::createARMMCSubtargetInfo);
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TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
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ARM_MC::createARMMCSubtargetInfo);
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// Register the MC instruction analyzer.
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TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
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createARMMCInstrAnalysis);
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TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
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createARMMCInstrAnalysis);
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// Register the MC Code Emitter
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TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
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TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
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// Register the asm backend.
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TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
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TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
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// Register the object streamer.
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TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
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TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
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// Register the asm streamer.
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TargetRegistry::RegisterAsmStreamer(TheARMTarget, createMCAsmStreamer);
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TargetRegistry::RegisterAsmStreamer(TheThumbTarget, createMCAsmStreamer);
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// Register the MCInstPrinter.
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TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
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TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
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// Register the MC relocation info.
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TargetRegistry::RegisterMCRelocationInfo(TheARMTarget,
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createARMMCRelocationInfo);
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TargetRegistry::RegisterMCRelocationInfo(TheThumbTarget,
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createARMMCRelocationInfo);
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}
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