Eli Friedman 7a5e55509b Slightly generalize the code that handles shuffles of consecutive loads ... on x86 to handle more cases. Fix a bug in said code that would cause it to read past the end of an object. Rewrite the code in SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. Remove PerformBuildVectorCombine, which is no longer necessary with these changes. In addition to simplifying the code, with this change, we can now catch a few more cases of consecutive loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73012 91177308-0d34-0410-b5e6-96231b3b80d8		2009-06-07 06:52:44 +00:00
..
Alpha
ARM	Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.	2009-06-05 19:08:58 +00:00
CBackend	Fix an erroneous check for isFNeg; the FNeg case is handled	2009-06-04 23:43:29 +00:00
CellSPU
CPP
Generic	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
IA64
Mips
MSP430
PowerPC	PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec	2009-06-07 01:07:55 +00:00
SPARC
X86	Slightly generalize the code that handles shuffles of consecutive loads	2009-06-07 06:52:44 +00:00
XCore