Robert Lytton 7b5376659c XCore target: add XCoreTargetLowering::isZExtFree() ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192431 91177308-0d34-0410-b5e6-96231b3b80d8

2013-10-11 10:26:29 +00:00

..

AArch64

Implement aarch64 neon instruction set AdvSIMD (copy).

2013-10-11 02:33:55 +00:00

ARM

Tests: Use CHECK-LABEL where possible

2013-10-10 22:37:47 +00:00

CPP

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Generic

Change objectsize intrinsic to accept different address spaces.

2013-10-07 18:06:48 +00:00

Hexagon

TBAA: remove !tbaa from testing cases when they are not needed.

2013-09-30 18:17:35 +00:00

Inputs

Debug Info: add an identifier field to DICompositeType.

2013-08-26 22:39:55 +00:00

Mips

[mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not intrinsics)

2013-10-11 10:14:25 +00:00

MSP430

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NVPTX

[NVPTX] Make constant vector test case endian-independent

2013-09-19 13:14:44 +00:00

PowerPC

TBAA: update tbaa format from scalar format to struct-path aware format.

2013-09-30 18:17:55 +00:00

R600

R600: Fix trunc i64 to i32 on SI

2013-10-10 18:04:16 +00:00

SPARC

[Sparc] Disable tail call optimization for sparc64.

2013-10-09 12:50:39 +00:00

SystemZ

[SystemZ] Add comparisons of high words and memory

2013-10-01 15:00:44 +00:00

Thumb

ARM: Use "dmb sy" for barriers on M-class CPUs

2013-08-28 14:39:19 +00:00

Thumb2

Fix spelling intruction -> instruction.

2013-09-28 11:46:15 +00:00

X86

Tests: Do not unnecessarily depend on kill comments

2013-10-10 22:37:49 +00:00

XCore

XCore target: add XCoreTargetLowering::isZExtFree()

2013-10-11 10:26:29 +00:00