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llvm-6502/lib/Target/SparcV8
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Brian Gaeke 7ba2a43866 Update current expected failures list - expand it to include all of 
SingleSource. Update to-do list (open-coding refers to binary operations on
longs, not to passing them into functions, which we already support.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17948 91177308-0d34-0410-b5e6-96231b3b80d8
2004-11-18 07:43:32 +00:00
..
DelaySlotFiller.cpp
Use TargetMachine::hasDelaySlot() instead of our old switch statement
2004-09-30 04:04:47 +00:00
FPMover.cpp
Pass which converts FpMOVD (double move pseudoinstructions) to pairs
2004-09-29 03:24:34 +00:00
Makefile
Change name of target lib to conform to new naming scheme.
2004-10-29 21:57:16 +00:00
README.txt
Update current expected failures list - expand it to include all of
2004-11-18 07:43:32 +00:00
SparcV8.h
Add createSparcV8FPMoverPass().
2004-09-29 03:25:39 +00:00
SparcV8.td
…
SparcV8AsmPrinter.cpp
Support UndefValue emission.
2004-11-14 03:22:05 +00:00
SparcV8CodeEmitter.cpp
* Add baseline structural JIT code, but disable the JIT to allow llvm-gcc builds
2004-10-19 19:49:42 +00:00
SparcV8InstrFormats.td
Class F2_1 already inherits the imm22 field from class F2
2004-10-14 22:32:24 +00:00
SparcV8InstrInfo.cpp
Recognize FpMOVD as a move.
2004-09-29 16:45:47 +00:00
SparcV8InstrInfo.h
…
SparcV8InstrInfo.td
Correct the implicit-defs information for indirect and direct calls.
2004-11-16 07:32:09 +00:00
SparcV8ISelSimple.cpp
We were (somehow) getting the wrong branch opcode for setcc float instrs.
2004-11-17 22:06:56 +00:00
SparcV8JITInfo.h
…
SparcV8RegisterInfo.cpp
Remove dependency on MRegisterInfo::getRegClass
2004-10-29 21:42:27 +00:00
SparcV8RegisterInfo.h
…
SparcV8RegisterInfo.td
Allocate fewer registers and tighten up alignment restrictions.
2004-11-18 00:25:20 +00:00
SparcV8TargetMachine.cpp
Allocate fewer registers and tighten up alignment restrictions.
2004-11-18 00:25:20 +00:00
SparcV8TargetMachine.h
Implement getModuleMatchQuality and getJITMatchQuality so that v8 will be the
2004-10-09 05:57:01 +00:00

README.txt 

SparcV8 backend skeleton
------------------------

This directory houses a 32-bit SPARC V8 backend employing a expander-based
instruction selector.  It is not yet functionally complete.  Watch
this space for more news coming soon!

Current expected test failures
------------------------------

All SingleSource/Benchmarks tests are expected to pass.  Currently, all
C++ tests and all tests involving varargs intrinsics (use of
va_start/va_end) are expected to fail.  Here are the known SingleSource
failures:

	UnitTests/SetjmpLongjmp/C++/C++Catch
	UnitTests/SetjmpLongjmp/C++/SimpleC++Test
	UnitTests/2003-05-07-VarArgs
	UnitTests/2003-07-09-SignedArgs
	UnitTests/2003-08-11-VaListArg
	Regression/C++/EH/ConditionalExpr
	Regression/C++/EH/ctor_dtor_count-2
	Regression/C++/EH/ctor_dtor_count
	Regression/C++/EH/exception_spec_test
	Regression/C++/EH/function_try_block
	Regression/C++/EH/simple_rethrow
	Regression/C++/EH/simple_throw
	Regression/C++/EH/throw_rethrow_test
	Regression/C/casts
	CustomChecked/oopack_v1p8

To-do
-----

* support setcc on longs
* support basic binary operations on longs
  - use libc procedures instead of open-coding for:
    __div64 __mul64 __rem64 __udiv64 __umul64 __urem64
* support casting 64-bit integers to FP types
* support varargs intrinsics (va_start et al.)

$Date$