llvm-6502/test/CodeGen
Robert Lytton 7c739380ee XCore target: change to Sched::Source
This sidesteps a bug in PrescheduleNodesWithMultipleUses() which
does not check if callResources will be affected by the transformation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190299 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 10:42:05 +00:00
..
AArch64 Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions, 2013-09-09 02:20:27 +00:00
ARM Debug Info Testing: update context from empty string to null. 2013-09-08 03:11:54 +00:00
CPP
Generic
Hexagon Debug Info Testing: use null instead of an empty string in context field. 2013-09-09 00:12:17 +00:00
Inputs
Mips [mips] Fix typos. 2013-09-07 01:14:42 +00:00
MSP430
NVPTX
PowerPC
R600
SPARC
SystemZ
Thumb
Thumb2
X86 Generate compact unwind encoding from CFI directives. 2013-09-09 02:37:14 +00:00
XCore XCore target: change to Sched::Source 2013-09-09 10:42:05 +00:00