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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
1.7 KiB
LLVM
63 lines
1.7 KiB
LLVM
; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC32
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; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC64
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declare void @foo()
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define i32 @test_cr2() nounwind uwtable {
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entry:
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%ret = alloca i32, align 4
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%0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmpw 2,$2,$1\0A\09mfcr $0", "=r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind
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store i32 %0, i32* %ret, align 4
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call void @foo()
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%1 = load i32, i32* %ret, align 4
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ret i32 %1
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}
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; PPC32: stw 31, -4(1)
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; PPC32: stwu 1, -32(1)
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; PPC32: mfcr 12
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; PPC32-NEXT: stw 12, 24(31)
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; PPC32: lwz 12, 24(31)
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; PPC32-NEXT: mtocrf 32, 12
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; PPC64: .cfi_startproc
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; PPC64: mfcr 12
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; PPC64: stw 12, 8(1)
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; PPC64: stdu 1, -[[AMT:[0-9]+]](1)
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; PPC64: .cfi_def_cfa_offset 128
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; PPC64: .cfi_offset lr, 16
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; PPC64: .cfi_offset cr2, 8
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; PPC64: addi 1, 1, [[AMT]]
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; PPC64: lwz 12, 8(1)
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; PPC64: mtocrf 32, 12
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; PPC64: .cfi_endproc
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define i32 @test_cr234() nounwind {
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entry:
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%ret = alloca i32, align 4
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%0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmpw 2,$2,$1\0A\09cmpw 3,$2,$2\0A\09cmpw 4,$2,$3\0A\09mfcr $0", "=r,r,r,r,r,~{cr2},~{cr3},~{cr4}"(i32 1, i32 2, i32 3, i32 0) nounwind
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store i32 %0, i32* %ret, align 4
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call void @foo()
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%1 = load i32, i32* %ret, align 4
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ret i32 %1
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}
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; PPC32: stw 31, -4(1)
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; PPC32: stwu 1, -32(1)
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; PPC32: mfcr 12
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; PPC32-NEXT: stw 12, 24(31)
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; PPC32: lwz 12, 24(31)
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; PPC32-NEXT: mtocrf 32, 12
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; PPC32-NEXT: mtocrf 16, 12
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; PPC32-NEXT: mtocrf 8, 12
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; PPC64: mfcr 12
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; PPC64: stw 12, 8(1)
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; PPC64: stdu 1, -[[AMT:[0-9]+]](1)
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; PPC64: addi 1, 1, [[AMT]]
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; PPC64: lwz 12, 8(1)
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; PPC64: mtocrf 32, 12
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; PPC64: mtocrf 16, 12
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; PPC64: mtocrf 8, 12
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