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llvm-6502/test/CodeGen/ARM
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Anton Korobeynikov 52237119a9 Initial support for some Thumb2 instructions. 
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17 18:13:58 +00:00
..
2006-11-10-CycleInDAG.ll
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2007-01-19-InfiniteLoop.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2007-01-31-RegInfoAssert.ll
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2007-02-02-JoinIntervalsCrash.ll
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2007-03-06-AddR7.ll
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2007-03-07-CombinerCrash.ll
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2007-03-13-InstrSched.ll
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2007-03-21-JoinIntervalsCrash.ll
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2007-03-26-RegScavengerAssert.ll
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2007-03-27-RegScavengerAssert.ll
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2007-03-30-RegScavengerAssert.ll
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2007-04-02-RegScavengerAssert.ll
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2007-04-03-PEIBug.ll
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2007-04-03-UndefinedSymbol.ll
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2007-04-30-CombinerCrash.ll
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2007-05-03-BadPostIndexedLd.ll
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2007-05-05-InvalidPushPop.ll
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2007-05-07-jumptoentry.ll
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2007-05-07-tailmerge-1.ll
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2007-05-09-tailmerge-2.ll
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2007-05-14-InlineAsmCstCrash.ll
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2007-05-14-RegScavengerAssert.ll
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2007-05-22-tailmerge-3.ll
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2007-05-23-BadPreIndexedStore.ll
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2007-05-31-RegScavengerInfiniteLoop.ll
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2007-08-15-ReuseBug.ll
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2008-02-04-LocalRegAllocBug.ll
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2008-02-29-RegAllocLocal.ll
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2008-03-05-SxtInRegBug.ll
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2008-03-07-RegScavengerAssert.ll
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2008-04-04-ScavengerAssert.ll
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2008-04-10-ScavengerAssert.ll
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2008-04-11-PHIofImpDef.ll
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2008-05-19-LiveIntervalsBug.ll
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2008-05-19-ScavengerAssert.ll
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2008-07-17-Fdiv.ll
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2008-07-24-CodeGenPrepCrash.ll
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2008-08-07-AsmPrintBug.ll
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2008-09-14-CoaleserBug.ll
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2008-09-17-CoalescerBug.ll
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2008-11-18-ScavengerAssert.ll
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2008-11-19-ScavengerAssert.ll
Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
2009-06-05 19:08:58 +00:00
2009-02-16-SpillerBug.ll
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2009-02-22-SoftenFloatVaArg.ll
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2009-02-27-SpillerBug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2009-03-07-SpillerBug.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2009-03-09-AddrModeBug.ll
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2009-04-06-AsmModifier.ll
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2009-04-08-AggregateAddr.ll
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2009-04-08-FloatUndef.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
2009-04-08-FREM.ll
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2009-04-09-RegScavengerAsm.ll
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2009-05-05-DAGCombineBug.ll
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2009-05-07-RegAllocLocal.ll
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2009-05-11-CodePlacementCrash.ll
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2009-05-18-InlineAsmMem.ll
Fix pr4091: Add support for "m" constraint in ARM inline assembly.
2009-05-19 05:53:42 +00:00
2009-06-04-MissingLiveIn.ll
A value defined by an implicit_def can be liven to a use BB. This is unfortunate. But register allocator still has to add it to the live-in set of the use BB.
2009-06-04 20:25:48 +00:00
2009-06-12-RegScavengerAssert.ll
If killed register is defined by implicit_def, do not clear it since it's live range may overlap another def of same register.
2009-06-12 21:34:26 +00:00
2009-06-15-RegScavengerAssert.ll
If a val# is defined by an implicit_def and it is being removed, all of the copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead.
2009-06-16 07:12:58 +00:00
addrmode.ll
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aliases.ll
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align.ll
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alloca.ll
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argaddr.ll
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arguments2.ll
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arguments3.ll
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arguments4.ll
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arguments5.ll
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arguments6.ll
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arguments7.ll
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arguments8.ll
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arguments_f64_backfill.ll
Add testcase for register scanveger assertion fix in r72755
2009-06-08 22:54:15 +00:00
arguments-nosplit-double.ll
Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and
2009-05-19 10:02:36 +00:00
arguments-nosplit-i64.ll
Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and
2009-05-19 10:02:36 +00:00
arguments.ll
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arm-asm.ll
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arm-negative-stride.ll
Add nounwind to a few tests.
2009-05-18 15:16:49 +00:00
bits.ll
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branch.ll
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bx_fold.ll
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call_nolink.ll
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call.ll
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clz.ll
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compare-call.ll
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constants.ll
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cse-libcalls.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
ctors_dtors.ll
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dg.exp
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div.ll
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dyn-stackalloc.ll
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extloadi1.ll
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fcopysign.ll
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fixunsdfdi.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
fmdrr-fmrrd.ll
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fnmul.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
formal.ll
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fp.ll
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fparith.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
fpcmp_ueq.ll
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fpcmp.ll
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fpconv.ll
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fpmem.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
fpow.ll
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fpowi.ll
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fptoint.ll
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frame_thumb.ll
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hello.ll
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hidden-vis-2.ll
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hidden-vis-3.ll
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hidden-vis.ll
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iabs.ll
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ifcvt1.ll
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ifcvt2.ll
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ifcvt3.ll
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ifcvt4.ll
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ifcvt5.ll
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ifcvt6.ll
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ifcvt7.ll
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ifcvt8.ll
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ifcvt9.ll
ifcvt should ignore cfg where true and false successors are the same.
2009-06-15 21:24:34 +00:00
illegal-vector-bitcast.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
imm.ll
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inlineasm2.ll
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inlineasm-imm-arm.ll
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inlineasm-imm-thumb.ll
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inlineasm.ll
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insn-sched1.ll
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ispositive.ll
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large-stack.ll
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ldm.ll
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ldr_ext.ll
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ldr_frame.ll
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ldr_post.ll
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ldr_pre.ll
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ldr.ll
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ldrd.ll
Part 1.
2009-06-15 08:28:29 +00:00
load-global.ll
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load.ll
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long_shift.ll
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long-setcc.ll
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long.ll
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lsr-code-insertion.ll
Mark some pattern-less instructions as neverHasSideEffects.
2009-06-12 20:46:18 +00:00
lsr-scale-addr-mode.ll
Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
2009-06-05 19:08:58 +00:00
mem.ll
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memcpy-inline.ll
Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
2009-06-05 19:08:58 +00:00
memfunc.ll
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mul.ll
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mulhi.ll
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mvn.ll
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pack.ll
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pr3502.ll
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private.ll
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remat.ll
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ret0.ll
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ret_arg1.ll
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ret_arg2.ll
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ret_arg3.ll
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ret_arg4.ll
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ret_arg5.ll
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ret_f32_arg2.ll
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ret_f32_arg5.ll
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ret_f64_arg2.ll
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ret_f64_arg_reg_split.ll
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ret_f64_arg_split.ll
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ret_f64_arg_stack.ll
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ret_i64_arg2.ll
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ret_i64_arg3.ll
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ret_i64_arg_split.ll
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ret_i128_arg2.ll
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ret_void.ll
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rev.ll
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section.ll
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select_xform.ll
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select.ll
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shifter_operand.ll
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smul.ll
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stack-frame.ll
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stm.ll
Add a ARM specific pre-allocation pass that re-schedule loads / stores from
2009-06-13 09:12:55 +00:00
str_post.ll
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str_pre-2.ll
Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.
2009-06-04 01:15:28 +00:00
str_pre.ll
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str_trunc.ll
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sxt_rot.ll
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thread_pointer.ll
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thumb2-add.ll
Initial support for some Thumb2 instructions.
2009-06-17 18:13:58 +00:00
thumb2-mov2.ll
Initial support for some Thumb2 instructions.
2009-06-17 18:13:58 +00:00
thumb2-mov.ll
Initial support for some Thumb2 instructions.
2009-06-17 18:13:58 +00:00
thumb2-shifter.ll
Initial support for some Thumb2 instructions.
2009-06-17 18:13:58 +00:00
thumb-imm.ll
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tls1.ll
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tls2.ll
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tls3.ll
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trunc_ldr.ll
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truncstore-dag-combine.ll
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tst_teq.ll
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uint64tof64.ll
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unaligned_load_store.ll
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unord.ll
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uxt_rot.ll
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uxtb.ll
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vargs2.ll
Make the test target-neutral
2009-06-16 20:25:25 +00:00
vargs_align.ll
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vargs.ll
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vfp.ll
Split the Add, Sub, and Mul instruction opcodes into separate
2009-06-04 22:49:04 +00:00
weak2.ll
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weak.ll
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