mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-12 03:32:10 +00:00
24732c3363
Before this patch we relied on the order of phi nodes when we looked for phi nodes of the same type. This could prevent vectorization of cases where there was a phi node of a second type in between phi nodes of some type. This is important for vectorization of an internal graphics kernel. On the test suite + external on x86_64 (and on a run on armv7s) it showed no impact on either performance or compile time. radar://15024459 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192537 91177308-0d34-0410-b5e6-96231b3b80d8
249 lines
8.0 KiB
LLVM
249 lines
8.0 KiB
LLVM
; RUN: opt < %s -basicaa -slp-vectorizer -slp-threshold=-100 -dce -S -mtriple=i386-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128"
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target triple = "i386-apple-macosx10.9.0"
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;int foo(double *A, int k) {
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; double A0;
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; double A1;
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; if (k) {
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; A0 = 3;
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; A1 = 5;
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; } else {
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; A0 = A[10];
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; A1 = A[11];
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; }
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; A[0] = A0;
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; A[1] = A1;
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;}
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;CHECK: i32 @foo
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;CHECK: load <2 x double>
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;CHECK: phi <2 x double>
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;CHECK: store <2 x double>
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;CHECK: ret i32 undef
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define i32 @foo(double* nocapture %A, i32 %k) {
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entry:
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%tobool = icmp eq i32 %k, 0
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br i1 %tobool, label %if.else, label %if.end
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if.else: ; preds = %entry
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%arrayidx = getelementptr inbounds double* %A, i64 10
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%0 = load double* %arrayidx, align 8
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%arrayidx1 = getelementptr inbounds double* %A, i64 11
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%1 = load double* %arrayidx1, align 8
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br label %if.end
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if.end: ; preds = %entry, %if.else
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%A0.0 = phi double [ %0, %if.else ], [ 3.000000e+00, %entry ]
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%A1.0 = phi double [ %1, %if.else ], [ 5.000000e+00, %entry ]
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store double %A0.0, double* %A, align 8
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%arrayidx3 = getelementptr inbounds double* %A, i64 1
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store double %A1.0, double* %arrayidx3, align 8
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ret i32 undef
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}
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;int foo(double * restrict B, double * restrict A, int n, int m) {
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; double R=A[1];
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; double G=A[0];
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; for (int i=0; i < 100; i++) {
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; R += 10;
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; G += 10;
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; R *= 4;
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; G *= 4;
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; R += 4;
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; G += 4;
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; }
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; B[0] = G;
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; B[1] = R;
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; return 0;
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;}
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;CHECK: foo2
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;CHECK: load <2 x double>
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;CHECK: phi <2 x double>
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;CHECK: fmul <2 x double>
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;CHECK: store <2 x double>
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;CHECK: ret
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define i32 @foo2(double* noalias nocapture %B, double* noalias nocapture %A, i32 %n, i32 %m) #0 {
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entry:
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%arrayidx = getelementptr inbounds double* %A, i64 1
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%0 = load double* %arrayidx, align 8
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%1 = load double* %A, align 8
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%i.019 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%G.018 = phi double [ %1, %entry ], [ %add5, %for.body ]
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%R.017 = phi double [ %0, %entry ], [ %add4, %for.body ]
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%add = fadd double %R.017, 1.000000e+01
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%add2 = fadd double %G.018, 1.000000e+01
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%mul = fmul double %add, 4.000000e+00
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%mul3 = fmul double %add2, 4.000000e+00
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%add4 = fadd double %mul, 4.000000e+00
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%add5 = fadd double %mul3, 4.000000e+00
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%inc = add nsw i32 %i.019, 1
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%exitcond = icmp eq i32 %inc, 100
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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store double %add5, double* %B, align 8
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%arrayidx7 = getelementptr inbounds double* %B, i64 1
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store double %add4, double* %arrayidx7, align 8
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ret i32 0
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}
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; float foo3(float *A) {
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;
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; float R = A[0];
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; float G = A[1];
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; float B = A[2];
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; float Y = A[3];
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; float P = A[4];
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; for (int i=0; i < 121; i+=3) {
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; R+=A[i+0]*7;
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; G+=A[i+1]*8;
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; B+=A[i+2]*9;
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; Y+=A[i+3]*10;
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; P+=A[i+4]*11;
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; }
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;
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; return R+G+B+Y+P;
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; }
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;CHECK: foo3
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;CHECK: phi <4 x float>
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;CHECK: fmul <4 x float>
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;CHECK: fadd <4 x float>
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;CHECK-NOT: phi <5 x float>
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;CHECK-NOT: fmul <5 x float>
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;CHECK-NOT: fadd <5 x float>
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define float @foo3(float* nocapture readonly %A) #0 {
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entry:
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%0 = load float* %A, align 4
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%arrayidx1 = getelementptr inbounds float* %A, i64 1
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%1 = load float* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds float* %A, i64 2
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%2 = load float* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds float* %A, i64 3
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%3 = load float* %arrayidx3, align 4
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%arrayidx4 = getelementptr inbounds float* %A, i64 4
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%4 = load float* %arrayidx4, align 4
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%P.056 = phi float [ %4, %entry ], [ %add26, %for.body ]
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%Y.055 = phi float [ %3, %entry ], [ %add21, %for.body ]
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%B.054 = phi float [ %2, %entry ], [ %add16, %for.body ]
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%G.053 = phi float [ %1, %entry ], [ %add11, %for.body ]
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%R.052 = phi float [ %0, %entry ], [ %add6, %for.body ]
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%5 = phi float [ %1, %entry ], [ %11, %for.body ]
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%6 = phi float [ %0, %entry ], [ %9, %for.body ]
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%mul = fmul float %6, 7.000000e+00
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%add6 = fadd float %R.052, %mul
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%mul10 = fmul float %5, 8.000000e+00
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%add11 = fadd float %G.053, %mul10
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%7 = add nsw i64 %indvars.iv, 2
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%arrayidx14 = getelementptr inbounds float* %A, i64 %7
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%8 = load float* %arrayidx14, align 4
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%mul15 = fmul float %8, 9.000000e+00
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%add16 = fadd float %B.054, %mul15
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 3
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%arrayidx19 = getelementptr inbounds float* %A, i64 %indvars.iv.next
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%9 = load float* %arrayidx19, align 4
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%mul20 = fmul float %9, 1.000000e+01
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%add21 = fadd float %Y.055, %mul20
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%10 = add nsw i64 %indvars.iv, 4
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%arrayidx24 = getelementptr inbounds float* %A, i64 %10
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%11 = load float* %arrayidx24, align 4
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%mul25 = fmul float %11, 1.100000e+01
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%add26 = fadd float %P.056, %mul25
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%12 = trunc i64 %indvars.iv.next to i32
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%cmp = icmp slt i32 %12, 121
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br i1 %cmp, label %for.body, label %for.end
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for.end: ; preds = %for.body
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%add28 = fadd float %add6, %add11
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%add29 = fadd float %add28, %add16
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%add30 = fadd float %add29, %add21
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%add31 = fadd float %add30, %add26
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ret float %add31
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}
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; Make sure the order of phi nodes of different types does not prevent
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; vectorization of same typed phi nodes.
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; CHECK-LABEL: sort_phi_type
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; CHECK: phi <4 x float>
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; CHECK: fmul <4 x float>
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define float @sort_phi_type(float* nocapture readonly %A) {
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%Y = phi float [ 1.000000e+01, %entry ], [ %mul10, %for.body ]
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%B = phi float [ 1.000000e+01, %entry ], [ %mul15, %for.body ]
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%G = phi float [ 1.000000e+01, %entry ], [ %mul20, %for.body ]
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%R = phi float [ 1.000000e+01, %entry ], [ %mul25, %for.body ]
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%mul10 = fmul float %Y, 8.000000e+00
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%mul15 = fmul float %B, 9.000000e+00
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%mul20 = fmul float %R, 10.000000e+01
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%mul25 = fmul float %G, 11.100000e+01
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%indvars.iv.next = add nsw i64 %indvars.iv, 4
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%cmp = icmp slt i64 %indvars.iv.next, 128
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br i1 %cmp, label %for.body, label %for.end
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for.end: ; preds = %for.body
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%add28 = fadd float 1.000000e+01, %mul10
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%add29 = fadd float %mul10, %mul15
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%add30 = fadd float %add29, %mul20
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%add31 = fadd float %add30, %mul25
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ret float %add31
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}
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define void @test(x86_fp80* %i1, x86_fp80* %i2, x86_fp80* %o) {
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; CHECK-LABEL: @test(
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;
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; Test that we correctly recognize the discontiguous memory in arrays where the
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; size is less than the alignment, and through various different GEP formations.
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;
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; We disable the vectorization of x86_fp80 for now.
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entry:
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%i1.0 = load x86_fp80* %i1, align 16
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%i1.gep1 = getelementptr x86_fp80* %i1, i64 1
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%i1.1 = load x86_fp80* %i1.gep1, align 16
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; CHECK: load x86_fp80*
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; CHECK: load x86_fp80*
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; CHECK-NOT: insertelement <2 x x86_fp80>
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; CHECK_NOT: insertelement <2 x x86_fp80>
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br i1 undef, label %then, label %end
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then:
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%i2.gep0 = getelementptr inbounds x86_fp80* %i2, i64 0
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%i2.0 = load x86_fp80* %i2.gep0, align 16
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%i2.gep1 = getelementptr inbounds x86_fp80* %i2, i64 1
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%i2.1 = load x86_fp80* %i2.gep1, align 16
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; CHECK: load x86_fp80*
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; CHECK: load x86_fp80*
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; CHECK-NOT: insertelement <2 x x86_fp80>
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; CHECK-NOT: insertelement <2 x x86_fp80>
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br label %end
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end:
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%phi0 = phi x86_fp80 [ %i1.0, %entry ], [ %i2.0, %then ]
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%phi1 = phi x86_fp80 [ %i1.1, %entry ], [ %i2.1, %then ]
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; CHECK-NOT: phi <2 x x86_fp80>
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; CHECK-NOT: extractelement <2 x x86_fp80>
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; CHECK-NOT: extractelement <2 x x86_fp80>
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store x86_fp80 %phi0, x86_fp80* %o, align 16
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%o.gep1 = getelementptr inbounds x86_fp80* %o, i64 1
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store x86_fp80 %phi1, x86_fp80* %o.gep1, align 16
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ret void
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}
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