mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-23 20:29:30 +00:00
e2a9376b1b
Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
112 lines
2.8 KiB
TableGen
112 lines
2.8 KiB
TableGen
//===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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def HasMSA : Predicate<"Subtarget.hasMSA()">,
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AssemblerPredicate<"FeatureMSA">;
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class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
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let Predicates = [HasMSA];
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let Inst{31-26} = 0b011110;
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}
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class PseudoMSA<dag outs, dag ins, list<dag> pattern,
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InstrItinClass itin = IIPseudo>:
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MipsPseudo<outs, ins, pattern, itin> {
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let Predicates = [HasMSA];
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}
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class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
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let Inst{25-23} = major;
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let Inst{22-19} = 0b1110;
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let Inst{5-0} = minor;
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}
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class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
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let Inst{25-23} = major;
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let Inst{22-20} = 0b110;
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let Inst{5-0} = minor;
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}
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class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
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let Inst{25-23} = major;
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let Inst{22-21} = 0b10;
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let Inst{5-0} = minor;
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}
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class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
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let Inst{25-23} = major;
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let Inst{22} = 0b0;
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let Inst{5-0} = minor;
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}
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class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
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let Inst{25-18} = major;
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let Inst{17-16} = df;
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let Inst{5-0} = minor;
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}
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class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
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let Inst{25-17} = major;
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let Inst{16} = df;
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let Inst{5-0} = minor;
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}
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class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
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let Inst{25-23} = major;
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let Inst{22-21} = df;
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let Inst{5-0} = minor;
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}
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class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
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let Inst{25-22} = major;
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let Inst{21} = df;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
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let Inst{25-22} = major;
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let Inst{21-20} = 0b00;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
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let Inst{25-22} = major;
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let Inst{21-19} = 0b100;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
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let Inst{25-22} = major;
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let Inst{21-18} = 0b1100;
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let Inst{5-0} = minor;
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}
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class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
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let Inst{25-22} = major;
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let Inst{21-17} = 0b11100;
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let Inst{5-0} = minor;
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}
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class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
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let Inst{25-23} = major;
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let Inst{22-21} = df;
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let Inst{5-0} = minor;
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}
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class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
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let Inst{25-24} = major;
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let Inst{5-0} = minor;
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}
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class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
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let Inst{25-23} = major;
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let Inst{22-21} = df;
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let Inst{5-0} = minor;
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}
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