Bill Wendling 8129d21396 When getting the number of bits necessary for addressing mode ...

ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141529 91177308-0d34-0410-b5e6-96231b3b80d8

2011-10-10 07:24:23 +00:00

..

Alpha

Convert more tests over to the new atomic instructions.

2011-09-26 21:30:17 +00:00

ARM

Reenable tail calls for iOS 5.0 and later.

2011-10-07 17:17:49 +00:00

Blackfin

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CBackend

Only run tests in test/CodeGen/CBackend/X86 when both X86 and CBackend are supported

2011-09-26 06:44:27 +00:00

CellSPU

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CPP

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Generic

PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval

2011-09-26 06:13:20 +00:00

MBlaze

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Mips

Move CHECK after entry label.

2011-10-03 21:24:30 +00:00

MSP430

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PowerPC

Convert more tests over to the new atomic instructions.

2011-09-26 21:30:17 +00:00

PTX

PTX: Add new patterns for bitconvert and any_extend

2011-09-29 01:13:12 +00:00

SPARC

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SystemZ

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Thumb

When getting the number of bits necessary for addressing mode

2011-10-10 07:24:23 +00:00

Thumb2

ARM Darwin default relocation model is PIC.

2011-09-30 17:41:35 +00:00

X86

Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.

2011-10-08 18:28:28 +00:00

XCore

Associate a MemOperand with LDWCP nodes introduced during ISel.

2011-09-12 14:43:23 +00:00