llvm-6502/test/CodeGen
Chad Rosier 1eb67a4f84 [AArch64] Add SchedRW lists to NEON instructions.
Previously, only regular AArch64 instructions were annotated with SchedRW lists.
This patch does the same for NEON enabling these instructions to be scheduled by
the MIScheduler. Additionally, store operations are now modeled and a few
SchedRW lists were updated for bug fixes (e.g. multiple def operands).

Reviewers: apazos, mcrosier, atrick
Patch by Dave Estes <cestes@codeaurora.org>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204505 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-21 19:34:41 +00:00
..
AArch64 [AArch64] Add SchedRW lists to NEON instructions. 2014-03-21 19:34:41 +00:00
ARM Fix test command line to avoid generating output file. 2014-03-21 07:20:29 +00:00
CPP
Generic CommandLine: Exit successfully for -version and -help 2014-02-28 19:08:01 +00:00
Hexagon
Inputs
Mips [mips] Correct lowering of VECTOR_SHUFFLE to VSHF. 2014-03-21 16:56:51 +00:00
MSP430
NVPTX Expose "noduplicate" attribute as a property for intrinsics. 2014-03-18 23:51:07 +00:00
PowerPC Remove redundant test. 2014-03-21 18:00:51 +00:00
R600 R600/SI: Move instruction patterns to scalar versions. 2014-03-21 18:01:18 +00:00
SPARC Remove the linker_private and linker_private_weak linkages. 2014-03-13 23:18:37 +00:00
SystemZ [SystemZ] Add support for z196 float<->unsigned conversions 2014-03-21 10:56:30 +00:00
Thumb
Thumb2
X86 Move codegen test over to MC. 2014-03-21 17:55:34 +00:00
XCore [XCore] Add support for the "m" inline asm constraint. 2014-03-06 16:37:48 +00:00