Akira Hatanaka 3531db14c6 [mips] Define register class FGRH32 for the high half of the 64-bit floating ... point registers. We will need this register class later when we add definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188842 91177308-0d34-0410-b5e6-96231b3b80d8		2013-08-20 22:58:56 +00:00
..
Analysis	Teach ConstantFolding about pointer address spaces	2013-08-20 21:20:04 +00:00
AsmParser
Bitcode
CodeGen	[SystemZ] Use SRST to optimize memchr	2013-08-20 09:38:48 +00:00
DebugInfo	llvm-dwarfdump: Do not include address offsets for attributes, only for tags	2013-08-19 03:36:23 +00:00
ExecutionEngine	memcmp is not a valid way to compare structs with padding in them.	2013-08-20 09:27:31 +00:00
IR	Introduce non-const overloads for GlobalAlias::{get,resolve}AliasedGlobal.	2013-08-19 23:13:33 +00:00
IRReader
Linker
MC	Fix style issues in AsmParser.cpp	2013-08-20 13:33:18 +00:00
Object	Add back missing PPC relocation types.	2013-08-09 09:42:14 +00:00
Option	Options: explicit handling of --	2013-08-13 22:23:05 +00:00
Support	Go through the really awkward dance required to delete the memory	2013-08-18 01:20:32 +00:00
TableGen	Add an error check for a typo I accidentally made in a td file that caused an assert to fire.	2013-08-20 04:22:09 +00:00
Target	[mips] Define register class FGRH32 for the high half of the 64-bit floating	2013-08-20 22:58:56 +00:00
Transforms	SLPVectorizer: Fix invalid iterator errors	2013-08-20 21:21:45 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile