Craig Topper 82a644adf2 Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201641 91177308-0d34-0410-b5e6-96231b3b80d8		2014-02-19 05:34:21 +00:00
..
avx-512.txt	AVX-512: decoder for AVX-512, made by Alexey Bader.	2013-12-25 11:40:51 +00:00
fp-stack.txt	Add two fp test cases I missed in my previous commit.	2013-12-31 23:15:19 +00:00
hex-immediates.txt
intel-syntax-32.txt
intel-syntax.txt
invalid-cmp-imm.txt
invalid-VEX-vvvv.txt
lit.local.cfg
marked-up.txt
moffs.txt	[x86] Fix disassembly of MOV16ao16 et al.	2014-01-20 12:02:53 +00:00
padlock.txt	Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.	2014-02-19 05:34:21 +00:00
prefixes.txt
simple-tests.txt	Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.	2014-01-01 15:29:32 +00:00
truncated-input.txt
x86-16.txt	[x86] Fix 16-bit disassembly of JCXZ/JECXZ	2014-01-20 12:02:48 +00:00
x86-32.txt	Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri.	2014-02-15 07:29:18 +00:00
x86-64.txt	Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860.	2014-02-17 10:03:43 +00:00