Mon P Wang 82c443655d Reintroduce support for overloading target intrinsics ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86114 91177308-0d34-0410-b5e6-96231b3b80d8

2009-11-05 03:19:08 +00:00

..

SubtargetFeature.h

Move DataTypes.h to include/llvm/System, update all users. This breaks the last

2009-10-26 01:35:46 +00:00

Target.td

Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a

2009-10-29 18:10:34 +00:00

TargetAsmParser.h

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TargetCallingConv.td

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TargetData.h

Move DataTypes.h to include/llvm/System, update all users. This breaks the last

2009-10-26 01:35:46 +00:00

TargetELFWriterInfo.h

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TargetFrameInfo.h

Use explicit structs instead of std::pair to map callee saved regs to spill slots.

2009-09-27 17:58:47 +00:00

TargetInstrDesc.h

Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a

2009-10-29 18:10:34 +00:00

TargetInstrInfo.h

Fix MachineLICM to use the correct virtual register class when

2009-10-30 22:18:41 +00:00

TargetInstrItineraries.h

Make the end-of-itinerary mark explicit. Some cleanup.

2009-09-24 20:22:50 +00:00

TargetIntrinsicInfo.h

Reintroduce support for overloading target intrinsics

2009-11-05 03:19:08 +00:00

TargetJITInfo.h

Move DataTypes.h to include/llvm/System, update all users. This breaks the last

2009-10-26 01:35:46 +00:00

TargetLowering.h

Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a

2009-10-29 18:10:34 +00:00

TargetLoweringObjectFile.h

Use OutStreamer.SwitchSection instead of writing out textual section directives.

2009-09-30 22:25:37 +00:00

TargetMachine.h

Add a CodeGenOpt::Less level to match -O1. It'll be used by clients which do not want post-regalloc scheduling.

2009-10-16 21:02:20 +00:00

TargetMachOWriterInfo.h

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TargetOptions.h

Implement the JIT side of the GDB JIT debugging interface. To enable this

2009-09-20 23:52:43 +00:00

TargetRegisterInfo.h

Adjust the scavenge register spilling to allow the target to choose an

2009-10-19 22:27:30 +00:00

TargetRegistry.h

Wire up the ARM MCInst printer, for llvm-mc.

2009-10-20 05:15:36 +00:00

TargetSchedule.td

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TargetSelect.h

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TargetSelectionDAG.td

Add a couple more target nodes

2009-11-03 03:30:51 +00:00

TargetSubtarget.h

Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.

2009-10-22 23:19:17 +00:00