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			73 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			TableGen
		
	
	
	
	
	
			
		
		
	
	
			73 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			TableGen
		
	
	
	
	
	
| //===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===//
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| //
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| //                     The LLVM Compiler Infrastructure
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| //
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| // This file is distributed under the University of Illinois Open Source
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| // License. See LICENSE.TXT for details.
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| //
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| //===----------------------------------------------------------------------===//
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| //
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| //
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| //===----------------------------------------------------------------------===//
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| 
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| //===----------------------------------------------------------------------===//
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| // Target-independent interfaces which we are implementing
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| //===----------------------------------------------------------------------===//
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| 
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| include "llvm/Target/Target.td"
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| 
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| //===----------------------------------------------------------------------===//
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| // SPARC Subtarget features.
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| //
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|  
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| def FeatureV9
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|   : SubtargetFeature<"v9", "IsV9", "true",
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|                      "Enable SPARC-V9 instructions">;
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| def FeatureV8Deprecated
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|   : SubtargetFeature<"deprecated-v8", "V8DeprecatedInsts", "true",
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|                      "Enable deprecated V8 instructions in V9 mode">;
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| def FeatureVIS
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|   : SubtargetFeature<"vis", "IsVIS", "true",
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|                      "Enable UltraSPARC Visual Instruction Set extensions">;
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| 
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| //===----------------------------------------------------------------------===//
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| // Register File, Calling Conv, Instruction Descriptions
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| //===----------------------------------------------------------------------===//
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| 
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| include "SparcRegisterInfo.td"
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| include "SparcCallingConv.td"
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| include "SparcInstrInfo.td"
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| 
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| def SparcInstrInfo : InstrInfo;
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| 
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| //===----------------------------------------------------------------------===//
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| // SPARC processors supported.
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| //===----------------------------------------------------------------------===//
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| 
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| class Proc<string Name, list<SubtargetFeature> Features>
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|  : Processor<Name, NoItineraries, Features>;
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| 
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| def : Proc<"generic",         []>;
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| def : Proc<"v8",              []>;
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| def : Proc<"supersparc",      []>;
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| def : Proc<"sparclite",       []>;
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| def : Proc<"f934",            []>;
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| def : Proc<"hypersparc",      []>;
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| def : Proc<"sparclite86x",    []>;
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| def : Proc<"sparclet",        []>;
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| def : Proc<"tsc701",          []>;
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| def : Proc<"v9",              [FeatureV9]>;
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| def : Proc<"ultrasparc",      [FeatureV9, FeatureV8Deprecated]>;
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| def : Proc<"ultrasparc3",     [FeatureV9, FeatureV8Deprecated]>;
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| def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
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| 
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| 
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| //===----------------------------------------------------------------------===//
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| // Declare the target which we are implementing
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| //===----------------------------------------------------------------------===//
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| 
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| def Sparc : Target {
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|   // Pull in Instruction Info:
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|   let InstructionSet = SparcInstrInfo;
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| }
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