mirror of
https://github.com/c64scene-ar/llvm-6502.git
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13af222bab
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
1048 lines
34 KiB
C++
1048 lines
34 KiB
C++
//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an ARM MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "ARMInstPrinter.h"
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#include "MCTargetDesc/ARMBaseInfo.h"
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#include "MCTargetDesc/ARMAddressingModes.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define GET_INSTRUCTION_NAME
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#include "ARMGenAsmWriter.inc"
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/// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
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///
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/// getSORegOffset returns an integer from 0-31, representing '32' as 0.
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static unsigned translateShiftImm(unsigned imm) {
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if (imm == 0)
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return 32;
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return imm;
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}
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ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
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const MCSubtargetInfo &STI) :
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MCInstPrinter(MAI) {
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// Initialize the set of available features.
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setAvailableFeatures(STI.getFeatureBits());
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}
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StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
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return getInstructionName(Opcode);
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}
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void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << getRegisterName(RegNo);
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}
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void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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StringRef Annot) {
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unsigned Opcode = MI->getOpcode();
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// Check for MOVs and print canonical forms, instead.
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if (Opcode == ARM::MOVsr) {
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// FIXME: Thumb variants?
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const MCOperand &Dst = MI->getOperand(0);
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const MCOperand &MO1 = MI->getOperand(1);
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const MCOperand &MO2 = MI->getOperand(2);
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const MCOperand &MO3 = MI->getOperand(3);
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O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
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printSBitModifierOperand(MI, 6, O);
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printPredicateOperand(MI, 4, O);
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O << '\t' << getRegisterName(Dst.getReg())
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<< ", " << getRegisterName(MO1.getReg());
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O << ", " << getRegisterName(MO2.getReg());
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assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
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printAnnotation(O, Annot);
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return;
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}
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if (Opcode == ARM::MOVsi) {
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// FIXME: Thumb variants?
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const MCOperand &Dst = MI->getOperand(0);
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const MCOperand &MO1 = MI->getOperand(1);
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const MCOperand &MO2 = MI->getOperand(2);
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O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
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printSBitModifierOperand(MI, 5, O);
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printPredicateOperand(MI, 3, O);
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O << '\t' << getRegisterName(Dst.getReg())
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<< ", " << getRegisterName(MO1.getReg());
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if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
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printAnnotation(O, Annot);
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return;
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}
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O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
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printAnnotation(O, Annot);
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return;
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}
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// A8.6.123 PUSH
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if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP &&
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MI->getNumOperands() > 5) {
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// Should only print PUSH if there are at least two registers in the list.
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O << '\t' << "push";
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printPredicateOperand(MI, 2, O);
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if (Opcode == ARM::t2STMDB_UPD)
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O << ".w";
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O << '\t';
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printRegisterList(MI, 4, O);
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printAnnotation(O, Annot);
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return;
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}
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if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
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MI->getOperand(3).getImm() == -4) {
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O << '\t' << "push";
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printPredicateOperand(MI, 4, O);
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O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
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printAnnotation(O, Annot);
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return;
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}
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// A8.6.122 POP
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if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP &&
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MI->getNumOperands() > 5) {
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// Should only print POP if there are at least two registers in the list.
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O << '\t' << "pop";
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printPredicateOperand(MI, 2, O);
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if (Opcode == ARM::t2LDMIA_UPD)
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O << ".w";
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O << '\t';
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printRegisterList(MI, 4, O);
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printAnnotation(O, Annot);
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return;
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}
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if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
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MI->getOperand(4).getImm() == 4) {
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O << '\t' << "pop";
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printPredicateOperand(MI, 5, O);
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O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
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printAnnotation(O, Annot);
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return;
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}
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// A8.6.355 VPUSH
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if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP) {
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O << '\t' << "vpush";
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printPredicateOperand(MI, 2, O);
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O << '\t';
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printRegisterList(MI, 4, O);
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printAnnotation(O, Annot);
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return;
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}
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// A8.6.354 VPOP
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if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
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MI->getOperand(0).getReg() == ARM::SP) {
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O << '\t' << "vpop";
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printPredicateOperand(MI, 2, O);
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O << '\t';
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printRegisterList(MI, 4, O);
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printAnnotation(O, Annot);
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return;
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}
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if (Opcode == ARM::tLDMIA) {
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bool Writeback = true;
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unsigned BaseReg = MI->getOperand(0).getReg();
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for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
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if (MI->getOperand(i).getReg() == BaseReg)
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Writeback = false;
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}
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O << "\tldm";
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printPredicateOperand(MI, 1, O);
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O << '\t' << getRegisterName(BaseReg);
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if (Writeback) O << "!";
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O << ", ";
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printRegisterList(MI, 3, O);
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printAnnotation(O, Annot);
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return;
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}
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// Thumb1 NOP
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if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
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MI->getOperand(1).getReg() == ARM::R8) {
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O << "\tnop";
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printPredicateOperand(MI, 2, O);
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printAnnotation(O, Annot);
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return;
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}
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printInstruction(MI, O);
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printAnnotation(O, Annot);
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}
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void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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unsigned Reg = Op.getReg();
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O << getRegisterName(Reg);
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} else if (Op.isImm()) {
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O << '#' << Op.getImm();
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} else {
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assert(Op.isExpr() && "unknown operand kind in printOperand");
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// If a symbolic branch target was added as a constant expression then print
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// that address in hex.
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const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
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int64_t Address;
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if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
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O << "0x";
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O.write_hex(Address);
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}
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else {
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// Otherwise, just print the expression.
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O << *Op.getExpr();
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}
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}
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}
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void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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if (MO1.isExpr())
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O << *MO1.getExpr();
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else if (MO1.isImm())
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O << "[pc, #" << MO1.getImm() << "]";
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else
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llvm_unreachable("Unknown LDR label operand?");
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}
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// so_reg is a 4-operand unit corresponding to register forms of the A5.1
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// "Addressing Mode 1 - Data-processing operands" forms. This includes:
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// REG 0 0 - e.g. R5
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// REG REG 0,SH_OPC - e.g. R5, ROR R3
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// REG 0 IMM,SH_OPC - e.g. R5, LSL #3
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void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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const MCOperand &MO3 = MI->getOperand(OpNum+2);
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O << getRegisterName(MO1.getReg());
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// Print the shift opc.
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ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
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O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
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if (ShOpc == ARM_AM::rrx)
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return;
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O << ' ' << getRegisterName(MO2.getReg());
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assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
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}
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void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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O << getRegisterName(MO1.getReg());
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// Print the shift opc.
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ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
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O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
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if (ShOpc == ARM_AM::rrx)
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return;
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O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #2
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//===--------------------------------------------------------------------===//
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void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(Op);
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const MCOperand &MO2 = MI->getOperand(Op+1);
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const MCOperand &MO3 = MI->getOperand(Op+2);
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O << "[" << getRegisterName(MO1.getReg());
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if (!MO2.getReg()) {
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if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
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O << ", #"
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<< ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
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<< ARM_AM::getAM2Offset(MO3.getImm());
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O << "]";
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return;
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}
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O << ", "
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<< ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
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<< getRegisterName(MO2.getReg());
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if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
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O << ", "
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<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
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<< " #" << ShImm;
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O << "]";
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}
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void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(Op);
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const MCOperand &MO2 = MI->getOperand(Op+1);
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const MCOperand &MO3 = MI->getOperand(Op+2);
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O << "[" << getRegisterName(MO1.getReg()) << "], ";
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if (!MO2.getReg()) {
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unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
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O << '#'
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<< ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
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<< ImmOffs;
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return;
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}
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O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
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<< getRegisterName(MO2.getReg());
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if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
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O << ", "
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<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
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<< " #" << ShImm;
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}
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void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(Op);
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const MCOperand &MO2 = MI->getOperand(Op+1);
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O << "[" << getRegisterName(MO1.getReg()) << ", "
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<< getRegisterName(MO2.getReg()) << "]";
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}
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void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(Op);
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const MCOperand &MO2 = MI->getOperand(Op+1);
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O << "[" << getRegisterName(MO1.getReg()) << ", "
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<< getRegisterName(MO2.getReg()) << ", lsl #1]";
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}
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void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(Op);
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if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
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printOperand(MI, Op, O);
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return;
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}
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const MCOperand &MO3 = MI->getOperand(Op+2);
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unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
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if (IdxMode == ARMII::IndexModePost) {
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printAM2PostIndexOp(MI, Op, O);
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return;
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}
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printAM2PreOrOffsetIndexOp(MI, Op, O);
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}
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void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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if (!MO1.getReg()) {
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unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
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O << '#'
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<< ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
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<< ImmOffs;
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return;
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}
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O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
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<< getRegisterName(MO1.getReg());
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if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
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O << ", "
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<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
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<< " #" << ShImm;
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #3
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//===--------------------------------------------------------------------===//
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void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(Op);
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const MCOperand &MO2 = MI->getOperand(Op+1);
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const MCOperand &MO3 = MI->getOperand(Op+2);
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O << "[" << getRegisterName(MO1.getReg()) << "], ";
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if (MO2.getReg()) {
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O << (char)ARM_AM::getAM3Op(MO3.getImm())
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<< getRegisterName(MO2.getReg());
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return;
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}
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unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
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O << '#'
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<< ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
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<< ImmOffs;
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}
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void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(Op);
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const MCOperand &MO2 = MI->getOperand(Op+1);
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const MCOperand &MO3 = MI->getOperand(Op+2);
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O << '[' << getRegisterName(MO1.getReg());
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if (MO2.getReg()) {
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O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
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<< getRegisterName(MO2.getReg()) << ']';
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return;
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}
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if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
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O << ", #"
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<< ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
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<< ImmOffs;
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O << ']';
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}
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void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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const MCOperand &MO3 = MI->getOperand(Op+2);
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unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
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if (IdxMode == ARMII::IndexModePost) {
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printAM3PostIndexOp(MI, Op, O);
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return;
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}
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printAM3PreOrOffsetIndexOp(MI, Op, O);
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}
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void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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const MCOperand &MO1 = MI->getOperand(OpNum);
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const MCOperand &MO2 = MI->getOperand(OpNum+1);
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if (MO1.getReg()) {
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O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
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<< getRegisterName(MO1.getReg());
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return;
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}
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unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
|
|
O << '#'
|
|
<< ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
|
|
<< ImmOffs;
|
|
}
|
|
|
|
void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO = MI->getOperand(OpNum);
|
|
unsigned Imm = MO.getImm();
|
|
O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
|
|
}
|
|
|
|
void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
|
|
}
|
|
|
|
void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO = MI->getOperand(OpNum);
|
|
unsigned Imm = MO.getImm();
|
|
O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
|
|
}
|
|
|
|
|
|
void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
|
|
.getImm());
|
|
O << ARM_AM::getAMSubModeStr(Mode);
|
|
}
|
|
|
|
void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
|
printOperand(MI, OpNum, O);
|
|
return;
|
|
}
|
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
|
|
unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
|
|
unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
|
|
if (ImmOffs || Op == ARM_AM::sub) {
|
|
O << ", #"
|
|
<< ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
|
|
<< ImmOffs * 4;
|
|
}
|
|
O << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
if (MO2.getImm()) {
|
|
// FIXME: Both darwin as and GNU as violate ARM docs here.
|
|
O << ", :" << (MO2.getImm() << 3);
|
|
}
|
|
O << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
O << "[" << getRegisterName(MO1.getReg()) << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO = MI->getOperand(OpNum);
|
|
if (MO.getReg() == 0)
|
|
O << "!";
|
|
else
|
|
O << ", " << getRegisterName(MO.getReg());
|
|
}
|
|
|
|
void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO = MI->getOperand(OpNum);
|
|
uint32_t v = ~MO.getImm();
|
|
int32_t lsb = CountTrailingZeros_32(v);
|
|
int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
|
|
assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
|
|
O << '#' << lsb << ", #" << width;
|
|
}
|
|
|
|
void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned val = MI->getOperand(OpNum).getImm();
|
|
O << ARM_MB::MemBOptToString(val);
|
|
}
|
|
|
|
void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned ShiftOp = MI->getOperand(OpNum).getImm();
|
|
bool isASR = (ShiftOp & (1 << 5)) != 0;
|
|
unsigned Amt = ShiftOp & 0x1f;
|
|
if (isASR)
|
|
O << ", asr #" << (Amt == 0 ? 32 : Amt);
|
|
else if (Amt)
|
|
O << ", lsl #" << Amt;
|
|
}
|
|
|
|
void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned Imm = MI->getOperand(OpNum).getImm();
|
|
if (Imm == 0)
|
|
return;
|
|
assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
|
|
O << ", lsl #" << Imm;
|
|
}
|
|
|
|
void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned Imm = MI->getOperand(OpNum).getImm();
|
|
// A shift amount of 32 is encoded as 0.
|
|
if (Imm == 0)
|
|
Imm = 32;
|
|
assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
|
|
O << ", asr #" << Imm;
|
|
}
|
|
|
|
void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << "{";
|
|
for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
|
|
if (i != OpNum) O << ", ";
|
|
O << getRegisterName(MI->getOperand(i).getReg());
|
|
}
|
|
O << "}";
|
|
}
|
|
|
|
void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &Op = MI->getOperand(OpNum);
|
|
if (Op.getImm())
|
|
O << "be";
|
|
else
|
|
O << "le";
|
|
}
|
|
|
|
void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &Op = MI->getOperand(OpNum);
|
|
O << ARM_PROC::IModToString(Op.getImm());
|
|
}
|
|
|
|
void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &Op = MI->getOperand(OpNum);
|
|
unsigned IFlags = Op.getImm();
|
|
for (int i=2; i >= 0; --i)
|
|
if (IFlags & (1 << i))
|
|
O << ARM_PROC::IFlagsToString(1 << i);
|
|
|
|
if (IFlags == 0)
|
|
O << "none";
|
|
}
|
|
|
|
void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &Op = MI->getOperand(OpNum);
|
|
unsigned SpecRegRBit = Op.getImm() >> 4;
|
|
unsigned Mask = Op.getImm() & 0xf;
|
|
|
|
if (getAvailableFeatures() & ARM::FeatureMClass) {
|
|
switch (Op.getImm()) {
|
|
default: assert(0 && "Unexpected mask value!");
|
|
case 0: O << "apsr"; return;
|
|
case 1: O << "iapsr"; return;
|
|
case 2: O << "eapsr"; return;
|
|
case 3: O << "xpsr"; return;
|
|
case 5: O << "ipsr"; return;
|
|
case 6: O << "epsr"; return;
|
|
case 7: O << "iepsr"; return;
|
|
case 8: O << "msp"; return;
|
|
case 9: O << "psp"; return;
|
|
case 16: O << "primask"; return;
|
|
case 17: O << "basepri"; return;
|
|
case 18: O << "basepri_max"; return;
|
|
case 19: O << "faultmask"; return;
|
|
case 20: O << "control"; return;
|
|
}
|
|
}
|
|
|
|
// As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
|
|
// APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
|
|
if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
|
|
O << "APSR_";
|
|
switch (Mask) {
|
|
default: assert(0);
|
|
case 4: O << "g"; return;
|
|
case 8: O << "nzcvq"; return;
|
|
case 12: O << "nzcvqg"; return;
|
|
}
|
|
llvm_unreachable("Unexpected mask value!");
|
|
}
|
|
|
|
if (SpecRegRBit)
|
|
O << "SPSR";
|
|
else
|
|
O << "CPSR";
|
|
|
|
if (Mask) {
|
|
O << '_';
|
|
if (Mask & 8) O << 'f';
|
|
if (Mask & 4) O << 's';
|
|
if (Mask & 2) O << 'x';
|
|
if (Mask & 1) O << 'c';
|
|
}
|
|
}
|
|
|
|
void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
|
|
if (CC != ARMCC::AL)
|
|
O << ARMCondCodeToString(CC);
|
|
}
|
|
|
|
void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
|
|
O << ARMCondCodeToString(CC);
|
|
}
|
|
|
|
void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
if (MI->getOperand(OpNum).getReg()) {
|
|
assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
|
|
"Expect ARM CPSR register!");
|
|
O << 's';
|
|
}
|
|
}
|
|
|
|
void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << MI->getOperand(OpNum).getImm();
|
|
}
|
|
|
|
void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << "p" << MI->getOperand(OpNum).getImm();
|
|
}
|
|
|
|
void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << "c" << MI->getOperand(OpNum).getImm();
|
|
}
|
|
|
|
void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << "{" << MI->getOperand(OpNum).getImm() << "}";
|
|
}
|
|
|
|
void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << "#" << MI->getOperand(OpNum).getImm() * 4;
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned Imm = MI->getOperand(OpNum).getImm();
|
|
O << "#" << (Imm == 0 ? 32 : Imm);
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
// (3 - the number of trailing zeros) is the number of then / else.
|
|
unsigned Mask = MI->getOperand(OpNum).getImm();
|
|
unsigned CondBit0 = Mask >> 4 & 1;
|
|
unsigned NumTZ = CountTrailingZeros_32(Mask);
|
|
assert(NumTZ <= 3 && "Invalid IT mask!");
|
|
for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
|
|
bool T = ((Mask >> Pos) & 1) == CondBit0;
|
|
if (T)
|
|
O << 't';
|
|
else
|
|
O << 'e';
|
|
}
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(Op);
|
|
const MCOperand &MO2 = MI->getOperand(Op + 1);
|
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
|
printOperand(MI, Op, O);
|
|
return;
|
|
}
|
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
if (unsigned RegNum = MO2.getReg())
|
|
O << ", " << getRegisterName(RegNum);
|
|
O << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
|
|
unsigned Op,
|
|
raw_ostream &O,
|
|
unsigned Scale) {
|
|
const MCOperand &MO1 = MI->getOperand(Op);
|
|
const MCOperand &MO2 = MI->getOperand(Op + 1);
|
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
|
printOperand(MI, Op, O);
|
|
return;
|
|
}
|
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
if (unsigned ImmOffs = MO2.getImm())
|
|
O << ", #" << ImmOffs * Scale;
|
|
O << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
|
|
unsigned Op,
|
|
raw_ostream &O) {
|
|
printThumbAddrModeImm5SOperand(MI, Op, O, 1);
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
|
|
unsigned Op,
|
|
raw_ostream &O) {
|
|
printThumbAddrModeImm5SOperand(MI, Op, O, 2);
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
|
|
unsigned Op,
|
|
raw_ostream &O) {
|
|
printThumbAddrModeImm5SOperand(MI, Op, O, 4);
|
|
}
|
|
|
|
void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
printThumbAddrModeImm5SOperand(MI, Op, O, 4);
|
|
}
|
|
|
|
// Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
|
|
// register with shift forms.
|
|
// REG 0 0 - e.g. R5
|
|
// REG IMM, SH_OPC - e.g. R5, LSL #3
|
|
void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
unsigned Reg = MO1.getReg();
|
|
O << getRegisterName(Reg);
|
|
|
|
// Print the shift opc.
|
|
assert(MO2.isImm() && "Not a valid t2_so_reg value!");
|
|
ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
|
|
O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
|
|
if (ShOpc != ARM_AM::rrx)
|
|
O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
|
|
}
|
|
|
|
void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
|
|
printOperand(MI, OpNum, O);
|
|
return;
|
|
}
|
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
|
|
int32_t OffImm = (int32_t)MO2.getImm();
|
|
bool isSub = OffImm < 0;
|
|
// Special value for #-0. All others are normal.
|
|
if (OffImm == INT32_MIN)
|
|
OffImm = 0;
|
|
if (isSub)
|
|
O << ", #-" << -OffImm;
|
|
else if (OffImm > 0)
|
|
O << ", #" << OffImm;
|
|
O << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
|
|
int32_t OffImm = (int32_t)MO2.getImm();
|
|
// Don't print +0.
|
|
if (OffImm == INT32_MIN)
|
|
O << ", #-0";
|
|
else if (OffImm < 0)
|
|
O << ", #-" << -OffImm;
|
|
else if (OffImm > 0)
|
|
O << ", #" << OffImm;
|
|
O << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
|
|
int32_t OffImm = (int32_t)MO2.getImm() / 4;
|
|
// Don't print +0.
|
|
if (OffImm < 0)
|
|
O << ", #-" << -OffImm * 4;
|
|
else if (OffImm > 0)
|
|
O << ", #" << OffImm * 4;
|
|
O << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
if (MO2.getImm())
|
|
O << ", #" << MO2.getImm() * 4;
|
|
O << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
int32_t OffImm = (int32_t)MO1.getImm();
|
|
// Don't print +0.
|
|
if (OffImm < 0)
|
|
O << ", #-" << -OffImm;
|
|
else
|
|
O << ", #" << OffImm;
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
int32_t OffImm = (int32_t)MO1.getImm() / 4;
|
|
// Don't print +0.
|
|
if (OffImm != 0) {
|
|
O << ", ";
|
|
if (OffImm < 0)
|
|
O << "#-" << -OffImm * 4;
|
|
else if (OffImm > 0)
|
|
O << "#" << OffImm * 4;
|
|
}
|
|
}
|
|
|
|
void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO1 = MI->getOperand(OpNum);
|
|
const MCOperand &MO2 = MI->getOperand(OpNum+1);
|
|
const MCOperand &MO3 = MI->getOperand(OpNum+2);
|
|
|
|
O << "[" << getRegisterName(MO1.getReg());
|
|
|
|
assert(MO2.getReg() && "Invalid so_reg load / store address!");
|
|
O << ", " << getRegisterName(MO2.getReg());
|
|
|
|
unsigned ShAmt = MO3.getImm();
|
|
if (ShAmt) {
|
|
assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
|
|
O << ", lsl #" << ShAmt;
|
|
}
|
|
O << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
const MCOperand &MO = MI->getOperand(OpNum);
|
|
O << '#' << ARM_AM::getFPImmFloat(MO.getImm());
|
|
}
|
|
|
|
void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned EncodedImm = MI->getOperand(OpNum).getImm();
|
|
unsigned EltBits;
|
|
uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
|
|
O << "#0x";
|
|
O.write_hex(Val);
|
|
}
|
|
|
|
void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned Imm = MI->getOperand(OpNum).getImm();
|
|
O << "#" << Imm + 1;
|
|
}
|
|
|
|
void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
unsigned Imm = MI->getOperand(OpNum).getImm();
|
|
if (Imm == 0)
|
|
return;
|
|
O << ", ror #";
|
|
switch (Imm) {
|
|
default: assert (0 && "illegal ror immediate!");
|
|
case 1: O << "8"; break;
|
|
case 2: O << "16"; break;
|
|
case 3: O << "24"; break;
|
|
}
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << "[" << MI->getOperand(OpNum).getImm() << "]";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
// Normally, it's not safe to use register enum values directly with
|
|
// addition to get the next register, but for VFP registers, the
|
|
// sort order is guaranteed because they're all of the form D<n>.
|
|
O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
|
|
<< getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
// Normally, it's not safe to use register enum values directly with
|
|
// addition to get the next register, but for VFP registers, the
|
|
// sort order is guaranteed because they're all of the form D<n>.
|
|
O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
|
|
<< getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
|
|
<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
|
|
raw_ostream &O) {
|
|
// Normally, it's not safe to use register enum values directly with
|
|
// addition to get the next register, but for VFP registers, the
|
|
// sort order is guaranteed because they're all of the form D<n>.
|
|
O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
|
|
<< getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
|
|
<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
|
|
<< getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
|
|
}
|
|
|
|
void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
|
|
unsigned OpNum,
|
|
raw_ostream &O) {
|
|
// Normally, it's not safe to use register enum values directly with
|
|
// addition to get the next register, but for VFP registers, the
|
|
// sort order is guaranteed because they're all of the form D<n>.
|
|
O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
|
|
<< getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[]}";
|
|
}
|