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https://github.com/c64scene-ar/llvm-6502.git
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843ee2e6a4
Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
100 lines
3.8 KiB
C++
100 lines
3.8 KiB
C++
//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "Sparc.h"
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#include "SparcTargetMachine.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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extern "C" void LLVMInitializeSparcTarget() {
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// Register the target.
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RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
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RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
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}
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/// SparcTargetMachine ctor - Create an ILP32 architecture model
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///
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SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL,
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bool is64bit)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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Subtarget(TT, CPU, FS, is64bit),
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DataLayout(Subtarget.getDataLayout()),
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TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
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FrameLowering(Subtarget) {
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}
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namespace {
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/// Sparc Code Generator Pass Configuration Options.
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class SparcPassConfig : public TargetPassConfig {
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public:
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SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM,
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bool DisableVerifyFlag)
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: TargetPassConfig(TM, PM, DisableVerifyFlag) {}
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SparcTargetMachine &getSparcTargetMachine() const {
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return getTM<SparcTargetMachine>();
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}
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virtual bool addInstSelector();
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virtual bool addPreEmitPass();
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};
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} // namespace
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TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM,
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bool DisableVerify) {
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return new SparcPassConfig(this, PM, DisableVerify);
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}
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bool SparcPassConfig::addInstSelector() {
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PM.add(createSparcISelDag(getSparcTargetMachine()));
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return false;
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}
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/// addPreEmitPass - This pass may be implemented by targets that want to run
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/// passes immediately before machine code is emitted. This should return
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/// true if -print-machineinstrs should print out the code after the passes.
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bool SparcPassConfig::addPreEmitPass(){
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PM.add(createSparcFPMoverPass(getSparcTargetMachine()));
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PM.add(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
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return true;
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}
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void SparcV8TargetMachine::anchor() { }
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SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
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StringRef TT, StringRef CPU,
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StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
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}
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void SparcV9TargetMachine::anchor() { }
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SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
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StringRef TT, StringRef CPU,
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StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
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}
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