Michael Gottesman 8493edfb4b Converted an overly aggressive assert to a conditional check in AddCombineTo64bitMLAL.
Said assert assumes that ADDC will always have a glue node as its second
argument and is checked before we even know that we are actually performing the
relevant MLAL optimization. This is incorrect since on ARM we *CAN* codegen ADDC
with a use list based second argument. Thus to have both effects, I converted
the assert to a conditional check which if it fails we do not perform the
optimization.

In terms of tests I can not produce an ADDC from the IR level until I get in my
multiprecision optimization patch which is forthcoming. The tests for said patch
would cause this assert to fail implying that said tests will provide the
relevant tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-18 20:49:40 +00:00
2013-06-11 19:04:13 +00:00
2013-05-07 20:31:28 +00:00
2013-06-18 20:42:25 +00:00
2013-06-11 19:04:13 +00:00
2013-06-11 19:04:13 +00:00
2013-05-09 12:32:36 +00:00
2013-05-23 02:53:22 +00:00
2013-04-17 05:34:03 +00:00

Low Level Virtual Machine (LLVM)
================================

This directory and its subdirectories contain source code for the Low Level
Virtual Machine, a toolkit for the construction of highly optimized compilers,
optimizers, and runtime environments.

LLVM is open source software. You may freely distribute it under the terms of
the license agreement found in LICENSE.txt.

Please see the documentation provided in docs/ for further
assistance with LLVM, and in particular docs/GettingStarted.rst for getting
started with LLVM and docs/README.txt for an overview of LLVM's
documentation setup.

If you're writing a package for LLVM, see docs/Packaging.rst for our
suggestions.

Description
LLVM backend for 6502
Readme 277 MiB
Languages
C++ 48.7%
LLVM 38.5%
Assembly 10.2%
C 0.9%
Python 0.4%
Other 1.2%