Jakob Stoklund Olesen
864c8702ba
Also combine zext/sext into selects for ARM.
This turns common i1 patterns into predicated instructions:
(add (zext cc), x) -> (select cc (add x, 1), x)
(add (sext cc), x) -> (select cc (add x, -1), x)
For a function like:
unsigned f(unsigned s, int x) {
return s + (x>0);
}
We now produce:
cmp r1, #0
it gt
addgt.w r0, r0, #1
Instead of:
movs r2, #0
cmp r1, #0
it gt
movgt r2, #1
add r0, r2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-18 21:25:22 +00:00
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