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2b4ea795a2
Currently tblgen cannot tell which operands in the operand list are results so it assumes the first one is a result. This is bad. Ideally we would fix this by separating results from inputs, e.g. (res R32:$dst), (ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding 'let noResults = 1' is the workaround to tell tblgen that the instruction does not produces a result. It works for now since tblgen does not support instructions which produce multiple results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| .. | ||
| Alpha | ||
| CBackend | ||
| IA64 | ||
| PowerPC | ||
| Skeleton | ||
| Sparc | ||
| SparcV8 | ||
| SparcV9 | ||
| X86 | ||
| Makefile | ||
| MRegisterInfo.cpp | ||
| SubtargetFeature.cpp | ||
| Target.td | ||
| TargetData.cpp | ||
| TargetFrameInfo.cpp | ||
| TargetInstrInfo.cpp | ||
| TargetMachine.cpp | ||
| TargetMachineRegistry.cpp | ||
| TargetSchedInfo.cpp | ||
| TargetSchedule.td | ||
| TargetSelectionDAG.td | ||
| TargetSubtarget.cpp | ||