Evan Cheng 875913439c InstrEmitter::EmitSubregNode() optimize extract_subreg in this case: ...

r1025 = s/zext r1024, 4
r1026 = extract_subreg r1025, 4

to a copy:
r1026 = copy r1024

This is correct. However it uses TII->isCoalescableExtInstr() which can return
true for instructions which essentially does a sext_in_reg so this can end up
with an illegal copy where the source and destination register classes do not
match. Add a check to avoid it. Sorry, no test case possible at this time.

rdar://11849816


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160059 91177308-0d34-0410-b5e6-96231b3b80d8

2012-07-11 18:55:07 +00:00

..

CMakeLists.txt

llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.

2012-06-24 13:32:01 +00:00

DAGCombiner.cpp

Only apply the SETCC+SITOFP -> SELECTCC optimization when the SETCC returns an MVT::i1, i.e. before type legalization.

2012-07-11 06:38:55 +00:00

FastISel.cpp

Whitespace.

2012-07-06 17:44:22 +00:00

FunctionLoweringInfo.cpp

Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and

2012-06-28 00:05:13 +00:00

InstrEmitter.cpp

InstrEmitter::EmitSubregNode() optimize extract_subreg in this case:

2012-07-11 18:55:07 +00:00

InstrEmitter.h

Allow trailing physreg RegisterSDNode operands on non-variadic instructions.

2012-07-04 23:53:23 +00:00

LegalizeDAG.cpp

Rename many of the Tmp1, Tmp2, Tmp3 variables to names such as Chain, Value, Ptr, etc.

2012-07-11 11:02:16 +00:00

LegalizeFloatTypes.cpp

Convert assert(0) to llvm_unreachable

2012-02-05 08:31:47 +00:00

LegalizeIntegerTypes.cpp

Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall

2012-05-25 16:35:28 +00:00

LegalizeTypes.cpp

Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall

2012-05-25 16:35:28 +00:00

LegalizeTypes.h

DAG legalisation can now handle illegal fma vector types by scalarisation

2012-06-24 00:05:44 +00:00

LegalizeTypesGeneric.cpp

Remove unnecessary default cases in switches that cover all enum values.

2012-01-10 16:47:17 +00:00

LegalizeVectorOps.cpp

'Promote' vector [su]int_to_fp should widen elements.

2012-06-28 21:03:44 +00:00

LegalizeVectorTypes.cpp

DAG legalisation can now handle illegal fma vector types by scalarisation

2012-06-24 00:05:44 +00:00

LLVMBuild.txt

LLVMBuild: Remove trailing newline, which irked me.

2011-12-12 19:48:00 +00:00

Makefile

…

ResourcePriorityQueue.cpp

I'm introducing a new machine model to simultaneously allow simple

2012-07-07 04:00:00 +00:00

ScheduleDAGFast.cpp

Simplify some more getAliasSet callers.

2012-06-01 22:38:17 +00:00

ScheduleDAGRRList.cpp

sdsched: Use the right heuristics when -mcpu is not provided and we have no itinerary.

2012-06-05 03:44:34 +00:00

ScheduleDAGSDNodes.cpp

Reapply 155668: Fix the SD scheduler to avoid gluing the same node twice.

2012-04-28 01:03:23 +00:00

ScheduleDAGSDNodes.h

misched: API for minimum vs. expected latency.

2012-06-05 21:11:27 +00:00

ScheduleDAGVLIW.cpp

misched preparation: rename core scheduler methods for consistency.

2012-03-07 23:00:49 +00:00

SDNodeDbgValue.h

…

SDNodeOrdering.h

…

SelectionDAG.cpp

Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and

2012-06-28 00:05:13 +00:00

SelectionDAGBuilder.cpp

Reverted r156659, due to probable performance regressions, DenseMap should be used here:

2012-07-04 05:53:05 +00:00

SelectionDAGBuilder.h

Fix typos found by http://github.com/lyda/misspell-check

2012-06-02 10:20:22 +00:00

SelectionDAGDumper.cpp

Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and

2012-06-28 00:05:13 +00:00

SelectionDAGISel.cpp

Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and

2012-06-28 00:05:13 +00:00

SelectionDAGPrinter.cpp

Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and

2012-06-28 00:05:13 +00:00

TargetLowering.cpp

All cases are covered, no need for a default. This deals with the

2012-07-05 10:14:33 +00:00

TargetSelectionDAGInfo.cpp

…