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https://github.com/c64scene-ar/llvm-6502.git
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d04ec0c855
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152360 91177308-0d34-0410-b5e6-96231b3b80d8
92 lines
2.8 KiB
C++
92 lines
2.8 KiB
C++
//==- MachineScheduler.h - MachineInstr Scheduling Pass ----------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides a MachineSchedRegistry for registering alternative machine
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// schedulers. A Target may provide an alternative scheduler implementation by
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// implementing the following boilerplate:
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//
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// static ScheduleDAGInstrs *createCustomMachineSched(MachineSchedContext *C) {
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// return new CustomMachineScheduler(C);
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// }
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// static MachineSchedRegistry
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// SchedCustomRegistry("custom", "Run my target's custom scheduler",
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// createCustomMachineSched);
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//
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// Inside <Target>PassConfig:
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// enablePass(MachineSchedulerID);
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// MachineSchedRegistry::setDefault(createCustomMachineSched);
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//
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//===----------------------------------------------------------------------===//
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#ifndef MACHINESCHEDULER_H
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#define MACHINESCHEDULER_H
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#include "llvm/CodeGen/MachinePassRegistry.h"
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namespace llvm {
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class AliasAnalysis;
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class LiveIntervals;
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class MachineDominatorTree;
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class MachineLoopInfo;
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class ScheduleDAGInstrs;
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/// MachineSchedContext provides enough context from the MachineScheduler pass
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/// for the target to instantiate a scheduler.
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struct MachineSchedContext {
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MachineFunction *MF;
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const MachineLoopInfo *MLI;
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const MachineDominatorTree *MDT;
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const TargetPassConfig *PassConfig;
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AliasAnalysis *AA;
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LiveIntervals *LIS;
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MachineSchedContext(): MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {}
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};
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/// MachineSchedRegistry provides a selection of available machine instruction
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/// schedulers.
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class MachineSchedRegistry : public MachinePassRegistryNode {
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public:
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typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedContext *);
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// RegisterPassParser requires a (misnamed) FunctionPassCtor type.
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typedef ScheduleDAGCtor FunctionPassCtor;
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static MachinePassRegistry Registry;
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MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
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: MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
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Registry.Add(this);
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}
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~MachineSchedRegistry() { Registry.Remove(this); }
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// Accessors.
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//
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MachineSchedRegistry *getNext() const {
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return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
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}
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static MachineSchedRegistry *getList() {
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return (MachineSchedRegistry *)Registry.getList();
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}
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static ScheduleDAGCtor getDefault() {
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return (ScheduleDAGCtor)Registry.getDefault();
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}
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static void setDefault(ScheduleDAGCtor C) {
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Registry.setDefault((MachinePassCtor)C);
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}
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static void setListener(MachinePassRegistryListener *L) {
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Registry.setListener(L);
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}
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};
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} // namespace llvm
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#endif
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