llvm-6502

arm-tests.txt

ARM: Correct printing of pre-indexed operands.

2013-04-12 18:47:25 +00:00

arm-thumb-trustzone.txt

ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.

2013-04-10 12:08:35 +00:00

arm-trustzone.txt

ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.

2013-04-10 12:08:35 +00:00

basic-arm-instructions.txt

This is a simple patch that changes RRX and RRXS to accept all registers as operands.

2013-06-05 13:23:51 +00:00

fp-encoding.txt

ARM: add fstmx and fldmx instructions for assembly

2013-05-31 15:55:51 +00:00

hex-immediates.txt

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invalid-Bcc-thumb.txt

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invalid-BFI-arm.txt

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invalid-CPS2p-arm.txt

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invalid-CPS3p-arm.txt

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invalid-DMB-thumb.txt

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invalid-DSB-arm.txt

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invalid-FSTMX-arm.txt

ARM: add fstmx and fldmx instructions for assembly

2013-05-31 15:55:51 +00:00

invalid-hint-arm.txt

ARM: Fix encoding of hint instruction for Thumb.

2013-04-26 17:54:54 +00:00

invalid-hint-thumb.txt

ARM: Fix encoding of hint instruction for Thumb.

2013-04-26 17:54:54 +00:00

invalid-IT-CBNZ-thumb.txt

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invalid-IT-CC15.txt

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invalid-IT-thumb.txt

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invalid-LDC-form-arm.txt

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invalid-LDM-thumb.txt

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invalid-LDR_POST-arm.txt

s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL.

2013-04-30 09:00:12 +00:00

invalid-LDR_PRE-arm.txt

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invalid-LDRB_POST-arm.txt

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invalid-LDRD_PRE-thumb.txt

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invalid-LDRrs-arm.txt

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invalid-MCR-arm.txt

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invalid-MOVr-arm.txt

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invalid-MOVs-arm.txt

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invalid-MOVs-LSL-arm.txt

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invalid-MOVTi16-arm.txt

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invalid-MRRC2-arm.txt

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invalid-MSRi-arm.txt

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invalid-RFEorLDMIA-arm.txt

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invalid-SBFX-arm.txt

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invalid-SMLAD-arm.txt

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invalid-SRS-arm.txt

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invalid-STMIA_UPD-thumb.txt

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invalid-SXTB-arm.txt

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invalid-t2Bcc-thumb.txt

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invalid-t2LDRBT-thumb.txt

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invalid-t2LDREXD-thumb.txt

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invalid-t2LDRSHi8-thumb.txt

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invalid-t2LDRSHi12-thumb.txt

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invalid-t2PUSH-thumb.txt

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invalid-t2STR_POST-thumb.txt

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invalid-t2STRD_PRE-thumb.txt

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invalid-t2STREXB-thumb.txt

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invalid-t2STREXD-thumb.txt

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invalid-UMAAL-arm.txt

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invalid-VEXTd-arm.txt

ARM: fix VEXT encoding corner case

2013-05-31 13:47:25 +00:00

invalid-VLD1DUPq8_UPD-arm.txt

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invalid-VLD1LNd32_UPD-thumb.txt

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invalid-VLD3DUPd32_UPD-thumb.txt

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invalid-VLD4DUPd32_UPD-thumb.txt

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invalid-VLD4LNd32_UPD-thumb.txt

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invalid-VLDMSDB_UPD-arm.txt

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invalid-VQADD-arm.txt

Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).

2013-05-20 14:42:43 +00:00

invalid-VST1d8Twb_register-thumb.txt

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invalid-VST1LNd32_UPD-thumb.txt

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invalid-VST2b32_UPD-arm.txt

VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).

2013-05-20 14:57:05 +00:00

invalid-VST4LNd32_UPD-thumb.txt

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invalid-VST-arm.txt

VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).

2013-05-20 14:57:05 +00:00

ldrd-armv4.txt

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lit.local.cfg

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marked-up-thumb.txt

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memory-arm-instructions.txt

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neon-tests.txt

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neon.txt

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neont2.txt

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neont-VLD-reencoding.txt

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neont-VST-reencoding.txt

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thumb1.txt

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thumb2.txt

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thumb-MSR-MClass.txt

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thumb-printf.txt

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thumb-tests.txt

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unpredictable-ADC-arm.txt

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unpredictable-ADDREXT3-arm.txt

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unpredictable-AExtI-arm.txt

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unpredictable-AI1cmp-arm.txt

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unpredictable-BFI.txt

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unpredictable-LDR-arm.txt

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unpredictable-LDRD-arm.txt

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unpredictable-LSL-regform.txt

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unpredictable-MRRC2-arm.txt

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unpredictable-MRS-arm.txt

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unpredictable-MUL-arm.txt

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unpredictable-RSC-arm.txt

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unpredictable-SEL-arm.txt

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unpredictable-SHADD16-arm.txt

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unpredictable-SSAT-arm.txt

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unpredictable-STRBrs-arm.txt

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unpredictable-swp-arm.txt

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unpredictable-UQADD8-arm.txt

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unpredictables-thumb.txt

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vfp4.txt

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