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llvm-6502/lib/Target/R600
History
Tom Stellard 8a6b7df6f8 R600: Expand vector FABS 
NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27 21:23:39 +00:00
..
InstPrinter
R600/SI: Change formatting of printed registers.
2013-11-12 02:35:51 +00:00
MCTargetDesc
[weak vtables] Remove a bunch of weak vtables
2013-11-19 00:57:56 +00:00
TargetInfo
R600: Remove unnecessary include
2013-06-07 20:28:43 +00:00
AMDGPU.h
R600: Simplify handling of private address space
2013-10-22 18:19:10 +00:00
AMDGPU.td
R600: Enable the IR structurizer by default
2013-11-18 19:43:44 +00:00
AMDGPUAsmPrinter.cpp
Indentation fixes
2013-11-14 10:08:50 +00:00
AMDGPUAsmPrinter.h
Fix missing C++ mode comment
2013-11-10 01:03:59 +00:00
AMDGPUCallingConv.td
R600: Use function inputs to represent data stored in gpr
2013-11-11 22:10:24 +00:00
AMDGPUConvertToISA.cpp
…
AMDGPUFrameLowering.cpp
R600: Fix calculation of stack offset in AMDGPUFrameLowering
2013-06-07 20:52:05 +00:00
AMDGPUFrameLowering.h
…
AMDGPUInstrInfo.cpp
[weak vtables] Remove a bunch of weak vtables
2013-11-19 00:57:56 +00:00
AMDGPUInstrInfo.h
R600/SI: Implement spilling of SGPRs v5
2013-11-27 21:23:35 +00:00
AMDGPUInstrInfo.td
R600: Add support for ISD::FROUND
2013-11-27 21:23:20 +00:00
AMDGPUInstructions.td
R600/SI: Fixing handling of condition codes
2013-11-22 23:07:58 +00:00
AMDGPUIntrinsics.td
R600: Add support for GROUP_BARRIER instruction
2013-06-28 15:46:59 +00:00
AMDGPUISelDAGToDAG.cpp
R600/SI: Add support for private address space load/store
2013-11-13 23:36:50 +00:00
AMDGPUISelLowering.cpp
R600: Expand vector FABS
2013-11-27 21:23:39 +00:00
AMDGPUISelLowering.h
Add target hook to prevent folding some bitcasted loads.
2013-11-15 04:42:23 +00:00
AMDGPUMachineFunction.cpp
[weak vtables] Remove a bunch of weak vtables
2013-11-19 00:57:56 +00:00
AMDGPUMachineFunction.h
[weak vtables] Remove a bunch of weak vtables
2013-11-19 00:57:56 +00:00
AMDGPUMCInstLower.cpp
R600: Store disassembly in a special ELF section when feature +DumpCode is enabled.
2013-10-12 05:02:51 +00:00
AMDGPUMCInstLower.h
…
AMDGPURegisterInfo.cpp
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
2013-08-14 23:24:32 +00:00
AMDGPURegisterInfo.h
R600/SI: Add support for private address space load/store
2013-11-13 23:36:50 +00:00
AMDGPURegisterInfo.td
Make SubRegIndex size mandatory, following r183020.
2013-05-31 23:45:26 +00:00
AMDGPUSubtarget.cpp
R600: Enable the IR structurizer by default
2013-11-18 19:43:44 +00:00
AMDGPUSubtarget.h
R600: Add a SubtargetFeatture for disabling the ifcvt pass.
2013-11-18 19:43:33 +00:00
AMDGPUTargetMachine.cpp
R600: Enable the IR structurizer by default
2013-11-18 19:43:44 +00:00
AMDGPUTargetMachine.h
SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
2013-07-27 00:01:07 +00:00
AMDGPUTargetTransformInfo.cpp
SimplifyCFG: Use parallel-and and parallel-or mode to consolidate branch conditions
2013-07-27 00:01:07 +00:00
AMDILBase.td
R600: Move Subtarget feature definitions into AMDGPU.td
2013-06-07 20:28:49 +00:00
AMDILCFGStructurizer.cpp
R600: Fix a crash in the AMDILCFGStrucurizer
2013-11-18 19:43:38 +00:00
AMDILInstrInfo.td
R600: Enable -verify-machineinstrs in some tests.
2013-10-01 19:32:38 +00:00
AMDILIntrinsicInfo.cpp
R600: Rework subtarget info and remove AMDILDevice classes
2013-06-07 20:37:48 +00:00
AMDILIntrinsicInfo.h
…
AMDILIntrinsics.td
…
AMDILISelLowering.cpp
Make some arrays 'static const'
2013-07-15 06:39:13 +00:00
AMDILRegisterInfo.td
…
CMakeLists.txt
R600: Simplify handling of private address space
2013-10-22 18:19:10 +00:00
LLVMBuild.txt
…
Makefile
…
Processors.td
R600/SI: Add processor type for Hawaii
2013-11-14 23:46:00 +00:00
R600ClauseMergePass.cpp
R600: add a pass that merges clauses.
2013-10-01 19:32:58 +00:00
R600ControlFlowFinalizer.cpp
R600: Add IsExport bit to TableGen instruction definitions
2013-08-16 01:11:51 +00:00
R600Defines.h
R600: Add support for i8 and i16 local memory stores
2013-08-26 15:05:49 +00:00
R600EmitClauseMarkers.cpp
R600: Fix scheduling of instructions that use the LDS output queue
2013-11-15 00:12:45 +00:00
R600ExpandSpecialInstrs.cpp
R600: Fix scheduling of instructions that use the LDS output queue
2013-11-15 00:12:45 +00:00
R600InstrFormats.td
R600: Use SchedModel enum for is{Trans,Vector}Only functions
2013-09-04 19:53:30 +00:00
R600InstrInfo.cpp
R600: Implement TargetInstrInfo::isLegalToSplitMBBAt()
2013-11-22 00:41:08 +00:00
R600InstrInfo.h
R600: Implement TargetInstrInfo::isLegalToSplitMBBAt()
2013-11-22 00:41:08 +00:00
R600Instructions.td
R600: Add support for ISD::FROUND
2013-11-27 21:23:20 +00:00
R600Intrinsics.td
R600: Reenable llvm.R600.load.input/interp.input for compatibility
2013-11-12 16:26:47 +00:00
R600ISelLowering.cpp
R600: Fix scheduling of instructions that use the LDS output queue
2013-11-15 00:12:45 +00:00
R600ISelLowering.h
R600/SI: Add support for private address space load/store
2013-11-13 23:36:50 +00:00
R600MachineFunctionInfo.cpp
[weak vtables] Remove a bunch of weak vtables
2013-11-19 00:57:56 +00:00
R600MachineFunctionInfo.h
[weak vtables] Remove a bunch of weak vtables
2013-11-19 00:57:56 +00:00
R600MachineScheduler.cpp
R600: Fix scheduling of instructions that use the LDS output queue
2013-11-15 00:12:45 +00:00
R600MachineScheduler.h
R600: Fix scheduling of instructions that use the LDS output queue
2013-11-15 00:12:45 +00:00
R600OptimizeVectorRegisters.cpp
R600: Enable folding of inline literals into REQ_SEQUENCE instructions
2013-08-16 01:11:55 +00:00
R600Packetizer.cpp
R600: Simplify handling of private address space
2013-10-22 18:19:10 +00:00
R600RegisterInfo.cpp
R600: Fix scheduling of instructions that use the LDS output queue
2013-11-15 00:12:45 +00:00
R600RegisterInfo.h
R600: Fix scheduling of instructions that use the LDS output queue
2013-11-15 00:12:45 +00:00
R600RegisterInfo.td
R600: Simplify handling of private address space
2013-10-22 18:19:10 +00:00
R600Schedule.td
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
R600TextureIntrinsicsReplacer.cpp
R600: Coding style
2013-09-05 23:55:13 +00:00
SIAnnotateControlFlow.cpp
Add 'const' qualifiers to static const char* variables.
2013-07-16 01:17:10 +00:00
SIDefines.h
R600/SI: Prefer SALU instructions for bit shift operations
2013-11-13 23:36:37 +00:00
SIFixSGPRCopies.cpp
R600/SI: Fix illegal VGPR->SGPR copy inside of loop
2013-11-18 18:50:20 +00:00
SIInsertWaits.cpp
R600/SI: Add support for private address space load/store
2013-11-13 23:36:50 +00:00
SIInstrFormats.td
R600/SI: Prefer SALU instructions for bit shift operations
2013-11-13 23:36:37 +00:00
SIInstrInfo.cpp
R600/SI: Implement spilling of SGPRs v5
2013-11-27 21:23:35 +00:00
SIInstrInfo.h
R600/SI: Implement spilling of SGPRs v5
2013-11-27 21:23:35 +00:00
SIInstrInfo.td
R600/SI: Add support for private address space load/store
2013-11-13 23:36:50 +00:00
SIInstructions.td
R600/SI: Implement spilling of SGPRs v5
2013-11-27 21:23:35 +00:00
SIIntrinsics.td
R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback
2013-09-12 02:55:14 +00:00
SIISelLowering.cpp
R600/SI: Fixing handling of condition codes
2013-11-22 23:07:58 +00:00
SIISelLowering.h
R600/SI: Implement add i64, but do not yet enable.
2013-11-18 20:09:47 +00:00
SILowerControlFlow.cpp
R600/SI: Add support for private address space load/store
2013-11-13 23:36:50 +00:00
SIMachineFunctionInfo.cpp
R600/SI: Implement spilling of SGPRs v5
2013-11-27 21:23:35 +00:00
SIMachineFunctionInfo.h
R600/SI: Implement spilling of SGPRs v5
2013-11-27 21:23:35 +00:00
SIRegisterInfo.cpp
R600/SI: Fix moveToVALU when the first operand is VSrc.
2013-11-18 20:09:55 +00:00
SIRegisterInfo.h
R600/SI: Add support for private address space load/store
2013-11-13 23:36:50 +00:00
SIRegisterInfo.td
R600: Fix handling of vector kernel arguments
2013-10-23 00:44:32 +00:00
SISchedule.td
…
SITypeRewriter.cpp
R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics
2013-08-14 23:24:53 +00:00