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https://github.com/c64scene-ar/llvm-6502.git
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8b5527deef
Fold and/or of setcc's to double CMOV: (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2) (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2) When we can't use the CMOV instruction, it might increase branch mispredicts. When we can, or when there is no mispredict, this improves throughput and reduces register pressure. These can't be catched by generic combines, because the pattern can appear when legalizing some instructions (such as fcmp une). rdar://19767934 http://reviews.llvm.org/D7634 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231045 91177308-0d34-0410-b5e6-96231b3b80d8
265 lines
7.7 KiB
LLVM
265 lines
7.7 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -mtriple=x86_64-unknown-linux | FileCheck %s --check-prefix=CHECK --check-prefix=CMOV
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; RUN: llc < %s -asm-verbose=false -mtriple=i686-unknown-linux | FileCheck %s --check-prefix=CHECK --check-prefix=NOCMOV
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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; Test 2xCMOV patterns exposed after legalization.
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; One way to do that is with (select (fcmp une/oeq)), which gets
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; legalized to setp/setne.
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; CHECK-LABEL: test_select_fcmp_oeq_i32:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: cmovnel %esi, %edi
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; CMOV-NEXT: cmovpl %esi, %edi
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; CMOV-NEXT: movl %edi, %eax
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: flds 8(%esp)
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; NOCMOV-NEXT: flds 4(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 16(%esp), %eax
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; NOCMOV-NEXT: movl %eax, %ecx
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 12(%esp), %ecx
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %ecx, %eax
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%eax), %eax
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; NOCMOV-NEXT: retl
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define i32 @test_select_fcmp_oeq_i32(float %a, float %b, i32 %c, i32 %d) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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%r = select i1 %cmp, i32 %c, i32 %d
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ret i32 %r
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}
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; CHECK-LABEL: test_select_fcmp_oeq_i64:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: cmovneq %rsi, %rdi
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; CMOV-NEXT: cmovpq %rsi, %rdi
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; CMOV-NEXT: movq %rdi, %rax
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: flds 8(%esp)
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; NOCMOV-NEXT: flds 4(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 20(%esp), %ecx
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; NOCMOV-NEXT: movl %ecx, %eax
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 12(%esp), %eax
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %eax, %ecx
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%ecx), %eax
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; NOCMOV-NEXT: orl $4, %ecx
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; NOCMOV-NEXT: movl (%ecx), %edx
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; NOCMOV-NEXT: retl
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define i64 @test_select_fcmp_oeq_i64(float %a, float %b, i64 %c, i64 %d) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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%r = select i1 %cmp, i64 %c, i64 %d
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ret i64 %r
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}
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; CHECK-LABEL: test_select_fcmp_une_i64:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: cmovneq %rdi, %rsi
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; CMOV-NEXT: cmovpq %rdi, %rsi
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; CMOV-NEXT: movq %rsi, %rax
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: flds 8(%esp)
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; NOCMOV-NEXT: flds 4(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 12(%esp), %ecx
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; NOCMOV-NEXT: movl %ecx, %eax
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 20(%esp), %eax
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %eax, %ecx
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%ecx), %eax
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; NOCMOV-NEXT: orl $4, %ecx
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; NOCMOV-NEXT: movl (%ecx), %edx
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; NOCMOV-NEXT: retl
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define i64 @test_select_fcmp_une_i64(float %a, float %b, i64 %c, i64 %d) #0 {
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entry:
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%cmp = fcmp une float %a, %b
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%r = select i1 %cmp, i64 %c, i64 %d
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ret i64 %r
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}
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; CHECK-LABEL: test_select_fcmp_oeq_f64:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: movaps %xmm3, %xmm0
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; CMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm2, %xmm0
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; CMOV-NEXT: [[TBB1]]:
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; CMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm0, %xmm3
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; CMOV-NEXT: [[TBB2]]:
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; CMOV-NEXT: movaps %xmm3, %xmm0
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: flds 8(%esp)
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; NOCMOV-NEXT: flds 4(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 20(%esp), %eax
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; NOCMOV-NEXT: movl %eax, %ecx
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 12(%esp), %ecx
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %ecx, %eax
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: fldl (%eax)
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; NOCMOV-NEXT: retl
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define double @test_select_fcmp_oeq_f64(float %a, float %b, double %c, double %d) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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%r = select i1 %cmp, double %c, double %d
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ret double %r
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}
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; CHECK-LABEL: test_select_fcmp_oeq_v4i32:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: movaps %xmm3, %xmm0
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; CMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm2, %xmm0
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; CMOV-NEXT: [[TBB1]]:
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; CMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm0, %xmm3
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; CMOV-NEXT: [[TBB2]]:
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; CMOV-NEXT: movaps %xmm3, %xmm0
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: pushl %ebx
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; NOCMOV-NEXT: pushl %edi
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; NOCMOV-NEXT: pushl %esi
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; NOCMOV-NEXT: flds 24(%esp)
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; NOCMOV-NEXT: flds 20(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 44(%esp), %eax
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; NOCMOV-NEXT: movl %eax, %ecx
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 28(%esp), %ecx
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %ecx, %eax
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%eax), %eax
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; NOCMOV-NEXT: leal 48(%esp), %ecx
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; NOCMOV-NEXT: movl %ecx, %edx
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 32(%esp), %edx
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %edx, %ecx
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%ecx), %ecx
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; NOCMOV-NEXT: leal 52(%esp), %edx
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; NOCMOV-NEXT: movl %edx, %esi
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 36(%esp), %esi
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %esi, %edx
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%edx), %edx
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; NOCMOV-NEXT: leal 56(%esp), %esi
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; NOCMOV-NEXT: movl %esi, %ebx
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; NOCMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; NOCMOV-NEXT: leal 40(%esp), %ebx
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; NOCMOV-NEXT: [[TBB1]]:
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; NOCMOV-NEXT: movl 16(%esp), %edi
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; NOCMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; NOCMOV-NEXT: movl %ebx, %esi
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; NOCMOV-NEXT: [[TBB2]]:
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; NOCMOV-NEXT: movl (%esi), %esi
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; NOCMOV-NEXT: movl %esi, 12(%edi)
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; NOCMOV-NEXT: movl %edx, 8(%edi)
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; NOCMOV-NEXT: movl %ecx, 4(%edi)
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; NOCMOV-NEXT: movl %eax, (%edi)
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; NOCMOV-NEXT: popl %esi
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; NOCMOV-NEXT: popl %edi
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; NOCMOV-NEXT: popl %ebx
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; NOCMOV-NEXT: retl $4
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define <4 x i32> @test_select_fcmp_oeq_v4i32(float %a, float %b, <4 x i32> %c, <4 x i32> %d) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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%r = select i1 %cmp, <4 x i32> %c, <4 x i32> %d
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ret <4 x i32> %r
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}
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; Also make sure we catch the original code-sequence of interest:
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; CMOV: [[ONE_F32_LCPI:.LCPI.*]]:
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; CMOV-NEXT: .long 1065353216
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; CHECK-LABEL: test_zext_fcmp_une:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: movss [[ONE_F32_LCPI]](%rip), %xmm0
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; CMOV-NEXT: movaps %xmm0, %xmm1
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; CMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; CMOV-NEXT: xorps %xmm1, %xmm1
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; CMOV-NEXT: [[TBB1]]:
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; CMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm1, %xmm0
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; CMOV-NEXT: [[TBB2]]:
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; CMOV-NEXT: retq
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; NOCMOV: jne
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; NOCMOV: jp
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define float @test_zext_fcmp_une(float %a, float %b) #0 {
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entry:
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%cmp = fcmp une float %a, %b
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%conv1 = zext i1 %cmp to i32
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%conv2 = sitofp i32 %conv1 to float
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ret float %conv2
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}
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; CMOV: [[ONE_F32_LCPI:.LCPI.*]]:
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; CMOV-NEXT: .long 1065353216
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; CHECK-LABEL: test_zext_fcmp_oeq:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: xorps %xmm0, %xmm0
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; CMOV-NEXT: xorps %xmm1, %xmm1
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; CMOV-NEXT: jne [[TBB1:.LBB[0-9_]+]]
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; CMOV-NEXT: movss [[ONE_F32_LCPI]](%rip), %xmm1
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; CMOV-NEXT: [[TBB1]]:
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; CMOV-NEXT: jp [[TBB2:.LBB[0-9_]+]]
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; CMOV-NEXT: movaps %xmm1, %xmm0
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; CMOV-NEXT: [[TBB2]]:
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; CMOV-NEXT: retq
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; NOCMOV: jne
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; NOCMOV: jp
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define float @test_zext_fcmp_oeq(float %a, float %b) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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%conv1 = zext i1 %cmp to i32
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%conv2 = sitofp i32 %conv1 to float
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ret float %conv2
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}
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attributes #0 = { nounwind }
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