Juergen Ributzka 8c9a0319bb [FastISel][AArch64] Add support for more addressing modes. ... FastISel didn't take much advantage of the different addressing modes available to it on AArch64. This commit allows the ComputeAddress method to recognize more addressing modes that allows shifts and sign-/zero-extensions to be folded into the memory operation itself. For Example: lsl x1, x1, #3 --> ldr x0, [x0, x1, lsl #3] ldr x0, [x0, x1] sxtw x1, w1 lsl x1, x1, #3 --> ldr x0, [x0, x1, sxtw #3] ldr x0, [x0, x1] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215597 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-13 22:53:29 +00:00
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AArch64	[FastISel][AArch64] Add support for more addressing modes.	2014-08-13 22:53:29 +00:00
ARM	[FastISel] Let the target decide first if it wants to materialize a constant.	2014-08-13 22:08:02 +00:00
CPP
Generic
Hexagon	DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.	2014-08-06 00:21:25 +00:00
Inputs
Mips	Add support for scalarizing cttz_zero_undef	2014-08-10 22:49:54 +00:00
MSP430
NVPTX
PowerPC	[FastISel] Let the target decide first if it wants to materialize a constant.	2014-08-13 22:08:02 +00:00
R600	R600: Correctly set the src value offset for scalarized kernel args	2014-08-13 18:14:11 +00:00
SPARC
SystemZ
Thumb
Thumb2	ARM: do not generate BLX instructions on Cortex-M CPUs.	2014-08-06 11:13:14 +00:00
X86	[FastISel][X86] Add large code model support for materializing floating-point constants.	2014-08-13 22:25:35 +00:00
XCore