Tim Northover 8ca089df49 AArch64: fix LowerCONCAT_VECTORS for new CodeGen. ... The function was making too many assumptions about its input: 1. The NEON_VDUP optimisation was far too aggressive, assuming (I think) that the input would always be BUILD_VECTOR. 2. We were treating most unknown concats as legal (by returning Op rather than SDValue()). I think only concats of pairs of vectors are actually legal. http://llvm.org/PR19094 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203450 91177308-0d34-0410-b5e6-96231b3b80d8		2014-03-10 09:34:07 +00:00
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AArch64	AArch64: fix LowerCONCAT_VECTORS for new CodeGen.	2014-03-10 09:34:07 +00:00
ARM	Replace PROLOG_LABEL with a new CFI_INSTRUCTION.	2014-03-07 06:08:31 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Moved test file from test/MC/Mips to test/CodeGen/Mips.	2014-03-07 22:08:46 +00:00
MSP430
NVPTX
PowerPC	Fixup PPC Darwin i1 argument handling	2014-03-06 00:45:19 +00:00
R600	R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCC	2014-03-07 20:12:39 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	Revert r203230, "CodeGenPrep: sink extends of illegal types into use block."	2014-03-09 11:01:07 +00:00
XCore	[XCore] Add support for the "m" inline asm constraint.	2014-03-06 16:37:48 +00:00