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https://github.com/c64scene-ar/llvm-6502.git
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8ca7ac2a38
First ARMTargetParser FIXME, conservatively changing the way we parse CPUs in the back-end. Still not perfect, with a lot of special cases, but moving towards a more generic solution. Moving all logic to the target parser made some unwritten assumptions about architectures in Clang to break. I've added a lot of architectures required by Clang, and default to CPUs that Clang believes it should (and I agree). I've also added a lot of unit tests, with the correct CPU for each architecture, and Clang seems to be working correctly, too. It also became clear that using "unsigned ID" as the argument for the get methods makes it hard to know what ID, so I also changed the argument names to match the enum type names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237797 91177308-0d34-0410-b5e6-96231b3b80d8
126 lines
3.0 KiB
C++
126 lines
3.0 KiB
C++
//===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise hardware features such as
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// FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_SUPPORT_TARGETPARSER_H
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#define LLVM_SUPPORT_TARGETPARSER_H
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namespace llvm {
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class StringRef;
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// Target specific information into their own namespaces. These should be
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// generated from TableGen because the information is already there, and there
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// is where new information about targets will be added.
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// FIXME: To TableGen this we need to make some table generated files available
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// even if the back-end is not compiled with LLVM, plus we need to create a new
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// back-end to TableGen to create these clean tables.
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namespace ARM {
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// FPU names.
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enum FPUKind {
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FK_INVALID = 0,
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FK_VFP,
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FK_VFPV2,
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FK_VFPV3,
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FK_VFPV3_D16,
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FK_VFPV4,
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FK_VFPV4_D16,
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FK_FPV5_D16,
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FK_FP_ARMV8,
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FK_NEON,
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FK_NEON_VFPV4,
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FK_NEON_FP_ARMV8,
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FK_CRYPTO_NEON_FP_ARMV8,
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FK_SOFTVFP,
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FK_LAST
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};
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// Arch names.
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enum ArchKind {
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AK_INVALID = 0,
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AK_ARMV2,
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AK_ARMV2A,
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AK_ARMV3,
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AK_ARMV3M,
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AK_ARMV4,
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AK_ARMV4T,
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AK_ARMV5,
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AK_ARMV5T,
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AK_ARMV5TE,
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AK_ARMV6,
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AK_ARMV6J,
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AK_ARMV6K,
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AK_ARMV6T2,
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AK_ARMV6Z,
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AK_ARMV6ZK,
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AK_ARMV6M,
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AK_ARMV7,
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AK_ARMV7A,
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AK_ARMV7R,
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AK_ARMV7M,
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AK_ARMV8A,
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AK_ARMV8_1A,
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// Non-standard Arch names.
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AK_IWMMXT,
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AK_IWMMXT2,
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AK_XSCALE,
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AK_ARMV5E,
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AK_ARMV5TEJ,
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AK_ARMV6SM,
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AK_ARMV7L,
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AK_ARMV7S,
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AK_ARMV7EM,
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AK_LAST
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};
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// Arch extension modifiers for CPUs.
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enum ArchExtKind {
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AEK_INVALID = 0,
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AEK_CRC,
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AEK_CRYPTO,
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AEK_FP,
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AEK_HWDIV,
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AEK_MP,
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AEK_SEC,
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AEK_VIRT,
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AEK_LAST
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};
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} // namespace ARM
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// Target Parsers, one per architecture.
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class ARMTargetParser {
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static StringRef getFPUSynonym(StringRef FPU);
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static StringRef getArchSynonym(StringRef Arch);
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public:
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static StringRef getCanonicalArchName(StringRef Arch);
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// Information by ID
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static const char * getFPUName(unsigned FPUKind);
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static const char * getArchName(unsigned ArchKind);
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static unsigned getArchDefaultCPUArch(unsigned ArchKind);
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static const char * getArchDefaultCPUName(unsigned ArchKind);
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static const char * getArchExtName(unsigned ArchExtKind);
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static const char * getDefaultCPU(StringRef Arch);
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// Parser
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static unsigned parseFPU(StringRef FPU);
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static unsigned parseArch(StringRef Arch);
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static unsigned parseArchExt(StringRef ArchExt);
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static unsigned parseCPUArch(StringRef CPU);
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};
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} // namespace llvm
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#endif
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