mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-03 00:33:09 +00:00
5ffe38ef6a
fixups yet, and doesn't handle actually encoding operand values, but this is enough for llc -show-mc-encoding to show the base instruction encoding information, e.g.: mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6] stw r0, 8(r1) ; encoding: [0x90,0x00,0x00,0x00] stwu r1, -64(r1) ; encoding: [0x94,0x00,0x00,0x00] Ltmp0: lhz r4, 4(r3) ; encoding: [0xa0,0x00,0x00,0x00] cmplwi cr0, r4, 8 ; encoding: [0x28,0x00,0x00,0x00] beq cr0, LBB0_2 ; encoding: [0x40,0x00,0x00,0x00] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119116 91177308-0d34-0410-b5e6-96231b3b80d8
34 lines
984 B
CMake
34 lines
984 B
CMake
set(LLVM_TARGET_DEFINITIONS PPC.td)
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tablegen(PPCGenInstrNames.inc -gen-instr-enums)
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tablegen(PPCGenRegisterNames.inc -gen-register-enums)
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tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
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tablegen(PPCGenCodeEmitter.inc -gen-emitter)
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tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
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tablegen(PPCGenRegisterInfo.h.inc -gen-register-desc-header)
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tablegen(PPCGenRegisterInfo.inc -gen-register-desc)
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tablegen(PPCGenInstrInfo.inc -gen-instr-desc)
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tablegen(PPCGenDAGISel.inc -gen-dag-isel)
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tablegen(PPCGenCallingConv.inc -gen-callingconv)
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tablegen(PPCGenSubtarget.inc -gen-subtarget)
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add_llvm_target(PowerPCCodeGen
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PPCAsmPrinter.cpp
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PPCBranchSelector.cpp
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PPCCodeEmitter.cpp
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PPCHazardRecognizers.cpp
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PPCInstrInfo.cpp
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PPCISelDAGToDAG.cpp
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PPCISelLowering.cpp
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PPCFrameInfo.cpp
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PPCJITInfo.cpp
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PPCMCAsmInfo.cpp
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PPCMCCodeEmitter.cpp
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PPCMCInstLower.cpp
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PPCPredicates.cpp
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PPCRegisterInfo.cpp
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PPCSubtarget.cpp
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PPCTargetMachine.cpp
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PPCSelectionDAGInfo.cpp
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)
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