Craig Topper 8e121843c1 Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192566 91177308-0d34-0410-b5e6-96231b3b80d8		2013-10-14 01:42:32 +00:00
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AArch64
ARM	[ARM] Fix FP ABI attributes with no VFP enabled.	2013-10-11 16:03:43 +00:00
AsmParser
COFF
Disassembler	Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.	2013-10-14 01:42:32 +00:00
ELF
MachO
Markup
Mips
PowerPC
SystemZ
X86	Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.	2013-10-14 01:21:22 +00:00