mirror of
https://github.com/c64scene-ar/llvm-6502.git
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bed85ff010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13813 91177308-0d34-0410-b5e6-96231b3b80d8
454 lines
15 KiB
C++
454 lines
15 KiB
C++
//===- SimpleInstrSelEmitter.cpp - Generate a Simple Instruction Selector ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting an instruction selector
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//
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//
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//===----------------------------------------------------------------------===//
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#include "InstrInfoEmitter.h"
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#include "SimpleInstrSelEmitter.h"
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#include "CodeGenWrappers.h"
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#include "Record.h"
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#include "Support/Debug.h"
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#include "Support/StringExtras.h"
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#include <set>
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#include "Record.h"
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#include "Support/CommandLine.h"
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#include "llvm/System/Signals.h"
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#include "Support/FileUtilities.h"
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#include "CodeEmitterGen.h"
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#include "RegisterInfoEmitter.h"
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#include "InstrInfoEmitter.h"
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#include "InstrSelectorEmitter.h"
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#include "SimpleInstrSelEmitter.h"
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#include <algorithm>
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#include <cstdio>
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#include <fstream>
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#include <vector>
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namespace llvm {
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std::string FnDecs;
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// run - Emit the main instruction description records for the target...
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void SimpleInstrSelEmitter::run(std::ostream &OS) {
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// EmitSourceFileHeader("Mark's Instruction Selector for the X86 target", OS);
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// OS << "#include \"llvm/CodeGen/MachineInstrBuilder.h\"\n";
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// OS << "#include \"llvm/Constants.h\"\n";
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// OS << "#include \"llvm/DerivedTypes.h\"\n";
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// OS << "#include \"llvm/Function.h\"\n";
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// OS << "#include \"llvm/Instructions.h\"\n";
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// OS << "#include \"llvm/IntrinsicLowering.h\"\n";
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// OS << "#include \"llvm/Pass.h\"\n";
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// OS << "#include \"llvm/CodeGen/MachineConstantPool.h\"\n";
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// OS << "#include \"llvm/CodeGen/MachineFrameInfo.h\"\n";
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// OS << "#include \"llvm/CodeGen/MachineFunction.h\"\n";
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// OS << "#include \"llvm/CodeGen/MachineInstrBuilder.h\"\n";
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// OS << "#include \"llvm/CodeGen/SSARegMap.h\"\n";
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// OS << "#include \"llvm/Target/MRegisterInfo.h\"\n";
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// OS << "#include \"llvm/Target/TargetMachine.h\"\n";
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// OS << "#include \"llvm/Support/InstVisitor.h\"\n";
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// OS << "using namespace llvm;\n\n";
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FnDecs = "";
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// for each InstrClass
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std::vector<Record*> Recs = Records.getAllDerivedDefinitions("InstrClass");
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for (unsigned i = 0, e = Recs.size(); i != e; ++i) {
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std::string InstrClassName = Recs[i]->getName();
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OS << "// Generate BMI instructions for " << InstrClassName << "\n\n";
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OS << "void ISel::visit";
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OS << Recs[i]->getValueAsString("FunctionName");
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OS << "(" << Recs[i]->getValueAsString("InstructionName") << " &I)\n{" << "\n";
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// for each supported InstrSubclass
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OS << spacing() << "unsigned DestReg = getReg(I);\n";
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OS << spacing() << "unsigned Op0Reg = getReg(I.getOperand(0));\n";
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OS << spacing() << "unsigned Op1Reg = getReg(I.getOperand(1));\n";
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OS << spacing() << "Value *Op0Val = I.getOperand(0);\n";
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OS << spacing() << "Value *Op1Val = I.getOperand(1);\n";
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OS << spacing() << "MachineBasicBlock::iterator IP = BB->end();\n";
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OS << std::endl;
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ListInit *SupportedSubclasses = Recs[i]->getValueAsListInit("Supports");
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//OS << spacing() << InstrClassName << "Prep();" << "\n";
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//FnDecs += "void ISel::" + InstrClassName + "Prep() {\n\n}\n\n";
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std::vector<std::string> vi;
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// generate subclasses nested switch statements
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InstrSubclasses(OS, InstrClassName, InstrClassName, SupportedSubclasses, vi, 0);
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//OS << spacing() << InstrClassName << "Post();\n";
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//FnDecs += "void ISel::" + InstrClassName + "Post() {\n\n}\n\n";
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OS << "}\n";
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OS << "\n\n\n";
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} // for each instrclass
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// OS << "} //namespace\n";
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#if 0
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// print out function stubs
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OS << "\n\n\n//Functions\n\n" << FnDecs;
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// print out getsubclass() definitions
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std::vector<Record*> SubclassColRec = Records.getAllDerivedDefinitions("InstrSubclassCollection");
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for (unsigned j=0, m=SubclassColRec.getSize(); j!=m; ++j) {
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std::string SubclassName = SubclassColRec[j]->getName();
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FnDecs += "unsigned ISel::get" + SubclassName + "() {\n\n";
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ListInit* list = dynamic_cast<ListInit*>(SubclassColRec[j].getValueAsListInit("List"));
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for (unsigned k=0; n=list.getSize(); k!=n; ++k) {
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FnDecs += "}\n\n";
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}
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#endif
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} //run
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// find instructions that match all the subclasses (only support for 1 now)
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Record* SimpleInstrSelEmitter::findInstruction(std::ostream &OS, std::string cl, std::vector<std::string>& vi) {
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std::vector<Record*> Recs = Records.getAllDerivedDefinitions("TargInstrSet");
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for (unsigned i = 0, e = Recs.size(); i != e; ++i) {
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Record* thisClass = Recs[i]->getValueAsDef("Class");
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if (thisClass->getName() == cl) {
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// get the Subclasses this supports
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ListInit* SubclassList = Recs[i]->getValueAsListInit("List");
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bool Match = true;
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if (SubclassList->getSize() != vi.size())
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Match = false;
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// match the instruction's supported subclasses with the subclasses we are looking for
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for (unsigned j=0, f=SubclassList->getSize(); j!=f; ++j) {
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DefInit* SubclassDef = dynamic_cast<DefInit*>(SubclassList->getElement(j));
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Record* thisSubclass = SubclassDef->getDef();
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std::string searchingFor = vi[j];
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if (thisSubclass->getName() != searchingFor) {
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Match = false;
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}
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} // for each subclass list
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if (Match == true) { return Recs[i]; }
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} //if instrclass matches
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} // for all instructions
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// if no instructions found, return NULL
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return NULL;
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} //findInstruction
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Record* SimpleInstrSelEmitter::findRegister(std::ostream &OS, std::string regname) {
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std::vector<Record*> Recs = Records.getAllDerivedDefinitions("Register");
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for (unsigned i = 0, e = Recs.size(); i != e; ++i) {
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Record* thisReg = Recs[i];
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if (thisReg->getName() == regname) return Recs[i];
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}
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return NULL;
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}
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// handle "::" and "+" etc
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std::string SimpleInstrSelEmitter::formatRegister(std::ostream &OS, std::string regname) {
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std::string Reg;
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std::string suffix;
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int x = std::strcspn(regname.c_str(),"+-");
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// operate on text before "+" or "-", append it back at the end
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Reg = regname.substr(0,x);
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suffix = regname.substr(x,regname.length());
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unsigned int y = std::strcspn(Reg.c_str(),":");
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if (y == Reg.length()) { // does not contain "::"
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Record* RegRec = findRegister(OS,Reg);
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assert(RegRec && "Register not found!");
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if (RegRec->getValueAsString("Namespace") != "Virtual") {
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Reg = RegRec->getValueAsString("Namespace") + "::" + RegRec->getName();
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} else {
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Reg = RegRec->getName();
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}
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} // regular case
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// append + or - at the end again (i.e. X86::EAX+1)
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Reg = Reg + suffix;
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return Reg;
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}
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// take information in the instruction class and generate the correct BMI call
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void SimpleInstrSelEmitter::generateBMIcall(std::ostream &OS, std::string MBB, std::string IP, std::string Opcode, int NumOperands, ListInit &instroperands, ListInit &operands) {
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// find Destination Register
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StringInit* DestRegStr = dynamic_cast<StringInit*>(operands.getElement(0));
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std::string DestReg = formatRegister(OS,DestRegStr->getValue());
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OS << "BuildMI(";
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OS << MBB << ", ";
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OS << IP << ", ";
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OS << Opcode << ", ";
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OS << NumOperands;
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if (DestReg != "Pseudo") {
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OS << ", " << DestReg << ")";
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} else {
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OS << ")";
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}
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// handle the .add stuff
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for (unsigned i=0, e=instroperands.getSize(); i!=e; ++i) {
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DefInit* OpDef = dynamic_cast<DefInit*>(instroperands.getElement(i));
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StringInit* RegStr = dynamic_cast<StringInit*>(operands.getElement(i+1));
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Record* Op = OpDef->getDef();
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std::string opstr = Op->getValueAsString("Name");
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std::string regname;
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if (opstr == "Register") {
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regname = formatRegister(OS,RegStr->getValue());
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} else {
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regname = RegStr->getValue();
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}
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OS << ".add" << opstr << "(" << regname << ")";
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}
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OS << ";\n";
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} //generateBMIcall
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std::string SimpleInstrSelEmitter::spacing() {
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return globalSpacing;
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}
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std::string SimpleInstrSelEmitter::addspacing() {
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globalSpacing += " ";
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return globalSpacing;
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}
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std::string SimpleInstrSelEmitter::remspacing() {
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globalSpacing = globalSpacing.substr(0,globalSpacing.length()-2);
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return globalSpacing;
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}
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// recursively print out the subclasses of an instruction
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//
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void SimpleInstrSelEmitter::InstrSubclasses(std::ostream &OS, std::string prefix, std::string InstrClassName, ListInit* SupportedSubclasses, std::vector<std::string>& vi, unsigned depth) {
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if (depth >= SupportedSubclasses->getSize()) {
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return;
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}
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// get the subclass collection
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DefInit* InstrSubclassColl = dynamic_cast<DefInit*>(SupportedSubclasses->getElement(depth));
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Record* InstrSubclassRec = InstrSubclassColl->getDef();
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std::string SubclassName = InstrSubclassRec->getName();
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if (InstrSubclassRec->getValueAsString("PreCode") != "") {
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// OS << spacing() << prefix << "_" << Subclass->getName() << "_Prep();\n";
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OS << spacing() << InstrSubclassRec->getValueAsString("PreCode") << "\n\n";
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}
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OS << spacing() << "// Looping through " << SubclassName << "\n";
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OS << spacing() << "switch (" << SubclassName <<") {\n";
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addspacing();
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ListInit* SubclassList = InstrSubclassRec->getValueAsListInit("List");
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for (unsigned k=0, g = SubclassList->getSize(); k!=g; ++k) {
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DefInit* SubclassDef = dynamic_cast<DefInit*>(SubclassList->getElement(k));
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Record* Subclass = SubclassDef->getDef();
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OS << spacing() << "// " << prefix << "_" << Subclass->getName() << "\n";
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OS << spacing() << "case " << Subclass->getName() << ":\n";
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addspacing();
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OS << spacing() << "{\n";
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vi.push_back(Subclass->getName());
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// go down hierarchy
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InstrSubclasses(OS, prefix + "_" + Subclass->getName(), InstrClassName, SupportedSubclasses, vi, depth+1);
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// find the record that matches this
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Record *theInstructionSet = findInstruction(OS, InstrClassName, vi);
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// only print out the assertion if this is a leaf
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if ( (theInstructionSet == NULL) && (depth == (SupportedSubclasses->getSize() - 1)) ) {
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OS << spacing() << "assert(0 && \"No instructions defined for " << InstrClassName << " instructions of subclasses " << prefix << "_" << Subclass->getName() << "!\");" << "\n";
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} else if (theInstructionSet != NULL) {
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if (theInstructionSet->getValueAsString("PreCode") != "") {
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OS << spacing() << theInstructionSet->getValueAsString("PreCode") << "\n\n";
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}
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ListInit *theInstructions = theInstructionSet->getValueAsListInit("Instructions");
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ListInit *registerlists = theInstructionSet->getValueAsListInit("Operands"); // not necessarily registers anymore, but the name will stay for now
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for (unsigned l=0, h=theInstructions->getSize(); l!=h; ++l) {
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DefInit *theInstructionDef = dynamic_cast<DefInit*>(theInstructions->getElement(l));
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Record *theInstruction = theInstructionDef->getDef();
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ListInit *operands = theInstruction->getValueAsListInit("Params");
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OS << spacing();
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ListInit* registers = dynamic_cast<ListInit*>(registerlists->getElement(l));
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// handle virtual instructions here before going to generateBMIcall
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if (theInstruction->getValueAsString("Namespace") == "Virtual") {
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// create reg for different sizes
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std::string Instr = theInstruction->getName();
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StringInit* DestRegInit = dynamic_cast<StringInit*>(registers->getElement(0));
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std::string DestReg = DestRegInit->getValue();
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std::string theType;
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if (Instr == "NullInstruction") { } // do nothing
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else if (Instr == "CreateRegByte")
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OS << "unsigned " << DestReg << " = makeAnotherReg(Type::SByteTy);\n";
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else if (Instr == "CreateRegShort")
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OS << "unsigned " << DestReg << " = makeAnotherReg(Type::SShortTy);\n";
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else if (Instr == "CreateRegInt")
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OS << "unsigned " << DestReg << " = makeAnotherReg(Type::SIntTy);\n";
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else if (Instr == "CreateRegLong")
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OS << "unsigned " << DestReg << " = makeAnotherReg(Type::SLongTy);\n";
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else if (Instr == "CreateRegUByte")
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OS << "unsigned " << DestReg << " = makeAnotherReg(Type::UByteTy);\n";
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else if (Instr == "CreateRegUShort")
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OS << "unsigned " << DestReg << " = makeAnotherReg(Type::UShortTy);\n";
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else if (Instr == "CreateRegUInt")
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OS << "unsigned " << DestReg << " = makeAnotherReg(Type::UIntTy);\n";
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else if (Instr == "CreateRegULong")
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OS << "unsigned " << DestReg << " = makeAnotherReg(Type::ULongTy);\n";
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else if (Instr == "CreateRegFloat")
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OS << "unsigned " << DestReg << " = makeAnotherReg(Type::FloatTy);\n";
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else if (Instr == "CreateRegDouble")
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OS << "unsigned " << DestReg << " = makeAnotherReg(Type::DoubleTy);\n";
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else if (Instr == "CreateRegPointer")
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OS << "unsigned " << DestReg << " = makeAnotherReg(Type::PointerTy_;\n";
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else
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OS << "unsigned " << DestReg << " = makeAnotherReg(Type::SByteTy);\n"; // create a byte by default
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} else {
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std::string InstrName;
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if (theInstruction->getValueAsString("Namespace") != "Virtual") {
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InstrName = theInstruction->getValueAsString("Namespace") + "::" + theInstruction->getValueAsString("Name");
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} else {
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// shouldn't ever happen, virtual instrs should be caught before this
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InstrName = theInstruction->getValueAsString("Name");
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}
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generateBMIcall(OS, "*BB","IP",InstrName,theInstruction->getValueAsInt("NumOperands"),*operands,*registers);
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}
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}
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if (theInstructionSet->getValueAsString("PostCode") != "") {
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OS << spacing() << theInstructionSet->getValueAsString("PostCode") << "\n\n";
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}
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}
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if (InstrSubclassRec->getValueAsString("PostCode") != "") {
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//OS << spacing() << "// " << prefix << "_" << Subclass->getName() << "_Prep();\n";
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OS << spacing() << InstrSubclassRec->getValueAsString("PostCode") << "\n\n";
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}
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OS << spacing() << "break;\n";
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OS << spacing() << "}\n\n";
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remspacing();
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vi.pop_back();
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}
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// provide a default case for the switch
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OS << spacing() << "default:\n";
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OS << spacing() << " assert(0 && \"No instructions defined for " << InstrClassName << " instructions of subclasses " << prefix << "_" << SubclassName << "!\");" << "\n";
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OS << spacing() << " break;\n\n";
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remspacing();
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OS << spacing() << "}\n";
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}
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// ret br switch invoke unwind
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// add sub mul div rem setcc (eq ne lt gt le ge)
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// and or xor sbl sbr
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// malloc free alloca load store
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// getelementptr phi cast call vanext vaarg
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} // End llvm namespace
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