mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-08-15 06:29:05 +00:00
9105f66d6f
I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209576 91177308-0d34-0410-b5e6-96231b3b80d8
98 lines
2.5 KiB
LLVM
98 lines
2.5 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-none-linux-gnu -arm64-load-store-opt=0 | FileCheck %s
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declare void @callee_stack0()
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declare void @callee_stack8([8 x i32], i64)
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declare void @callee_stack16([8 x i32], i64, i64)
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define void @caller_to0_from0() nounwind {
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; CHECK-LABEL: caller_to0_from0:
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; CHECK-NEXT: // BB
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tail call void @callee_stack0()
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ret void
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; CHECK-NEXT: b callee_stack0
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}
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define void @caller_to0_from8([8 x i32], i64) nounwind{
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; CHECK-LABEL: caller_to0_from8:
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; CHECK-NEXT: // BB
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tail call void @callee_stack0()
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ret void
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; CHECK-NEXT: b callee_stack0
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}
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define void @caller_to8_from0() {
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; CHECK-LABEL: caller_to8_from0:
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; Caller isn't going to clean up any extra stack we allocate, so it
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; can't be a tail call.
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tail call void @callee_stack8([8 x i32] undef, i64 42)
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ret void
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; CHECK: bl callee_stack8
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}
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define void @caller_to8_from8([8 x i32], i64 %a) {
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; CHECK-LABEL: caller_to8_from8:
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; CHECK-NOT: sub sp, sp,
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; This should reuse our stack area for the 42
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tail call void @callee_stack8([8 x i32] undef, i64 42)
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ret void
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; CHECK: str {{x[0-9]+}}, [sp]
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; CHECK-NEXT: b callee_stack8
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}
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define void @caller_to16_from8([8 x i32], i64 %a) {
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; CHECK-LABEL: caller_to16_from8:
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; Shouldn't be a tail call: we can't use SP+8 because our caller might
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; have something there. This may sound obvious but implementation does
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; some funky aligning.
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tail call void @callee_stack16([8 x i32] undef, i64 undef, i64 undef)
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; CHECK: bl callee_stack16
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ret void
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}
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define void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: caller_to8_from24:
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; CHECK-NOT: sub sp, sp
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; Reuse our area, putting "42" at incoming sp
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tail call void @callee_stack8([8 x i32] undef, i64 42)
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ret void
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; CHECK: str {{x[0-9]+}}, [sp]
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; CHECK-NEXT: b callee_stack8
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}
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define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
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; CHECK-LABEL: caller_to16_from16:
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; CHECK-NOT: sub sp, sp,
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; Here we want to make sure that both loads happen before the stores:
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; otherwise either %a or %b will be wrongly clobbered.
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tail call void @callee_stack16([8 x i32] undef, i64 %b, i64 %a)
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ret void
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; CHECK: ldr [[VAL0:x[0-9]+]],
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; CHECK: ldr [[VAL1:x[0-9]+]],
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; CHECK: str [[VAL1]],
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; CHECK: str [[VAL0]],
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; CHECK-NOT: add sp, sp,
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; CHECK: b callee_stack16
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}
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@func = global void(i32)* null
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define void @indirect_tail() {
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; CHECK-LABEL: indirect_tail:
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; CHECK-NOT: sub sp, sp
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%fptr = load void(i32)** @func
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tail call void %fptr(i32 42)
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ret void
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; CHECK: ldr [[FPTR:x[1-9]+]], [{{x[0-9]+}}, {{#?}}:lo12:func]
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; CHECK: movz w0, #{{42|0x2a}}
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; CHECK: br [[FPTR]]
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}
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