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https://github.com/c64scene-ar/llvm-6502.git
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aa0cfea9a4
We don't have enough GR64_TC registers when calling a varargs function with 6 arguments. Since %al holds the number of vector registers used, only %r11 is available as a scratch register. This means that addressing modes using both base and index registers can't be folded into TCRETURNmi64. <rdar://problem/12282281> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163761 91177308-0d34-0410-b5e6-96231b3b80d8
131 lines
3.5 KiB
LLVM
131 lines
3.5 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs | FileCheck %s
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target datalayout = "e-p:64:64:64-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin11.4.0"
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declare i64 @testi()
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define i64 @test_trivial() {
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%A = tail call i64 @testi()
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ret i64 %A
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}
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; CHECK: test_trivial:
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; CHECK: jmp _testi ## TAILCALL
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define i64 @test_noop_bitcast() {
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%A = tail call i64 @testi()
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%B = bitcast i64 %A to i64
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ret i64 %B
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}
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; CHECK: test_noop_bitcast:
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; CHECK: jmp _testi ## TAILCALL
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; Tail call shouldn't be blocked by no-op inttoptr.
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define i8* @test_inttoptr() {
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%A = tail call i64 @testi()
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%B = inttoptr i64 %A to i8*
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ret i8* %B
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}
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; CHECK: test_inttoptr:
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; CHECK: jmp _testi ## TAILCALL
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declare <4 x float> @testv()
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define <4 x i32> @test_vectorbitcast() {
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%A = tail call <4 x float> @testv()
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%B = bitcast <4 x float> %A to <4 x i32>
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ret <4 x i32> %B
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}
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; CHECK: test_vectorbitcast:
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; CHECK: jmp _testv ## TAILCALL
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declare { i64, i64 } @testp()
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define {i64, i64} @test_pair_trivial() {
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%A = tail call { i64, i64} @testp()
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ret { i64, i64} %A
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}
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; CHECK: test_pair_trivial:
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; CHECK: jmp _testp ## TAILCALL
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define {i64, i64} @test_pair_trivial_extract() {
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%A = tail call { i64, i64} @testp()
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%x = extractvalue { i64, i64} %A, 0
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%y = extractvalue { i64, i64} %A, 1
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%b = insertvalue {i64, i64} undef, i64 %x, 0
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%c = insertvalue {i64, i64} %b, i64 %y, 1
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ret { i64, i64} %c
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}
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; CHECK: test_pair_trivial_extract:
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; CHECK: jmp _testp ## TAILCALL
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define {i8*, i64} @test_pair_conv_extract() {
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%A = tail call { i64, i64} @testp()
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%x = extractvalue { i64, i64} %A, 0
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%y = extractvalue { i64, i64} %A, 1
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%x1 = inttoptr i64 %x to i8*
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%b = insertvalue {i8*, i64} undef, i8* %x1, 0
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%c = insertvalue {i8*, i64} %b, i64 %y, 1
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ret { i8*, i64} %c
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}
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; CHECK: test_pair_conv_extract:
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; CHECK: jmp _testp ## TAILCALL
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; PR13006
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define { i64, i64 } @crash(i8* %this) {
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%c = tail call { i64, i64 } @testp()
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%mrv7 = insertvalue { i64, i64 } %c, i64 undef, 1
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ret { i64, i64 } %mrv7
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}
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; <rdar://problem/12282281> Fold an indexed load into the tail call instruction.
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; Calling a varargs function with 6 arguments requires 7 registers (%al is the
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; vector count for varargs functions). This leaves %r11 as the only available
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; scratch register.
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;
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; It is not possible to fold an indexed load into TCRETURNmi64 in that case.
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;
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; typedef int (*funcptr)(void*, ...);
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; extern const funcptr funcs[];
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; int f(int n) {
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; return funcs[n](0, 0, 0, 0, 0, 0);
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; }
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;
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; CHECK: rdar12282281
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; CHECK: jmpq *%r11 # TAILCALL
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@funcs = external constant [0 x i32 (i8*, ...)*]
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define i32 @rdar12282281(i32 %n) nounwind uwtable ssp {
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entry:
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%idxprom = sext i32 %n to i64
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%arrayidx = getelementptr inbounds [0 x i32 (i8*, ...)*]* @funcs, i64 0, i64 %idxprom
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%0 = load i32 (i8*, ...)** %arrayidx, align 8
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%call = tail call i32 (i8*, ...)* %0(i8* null, i32 0, i32 0, i32 0, i32 0, i32 0) nounwind
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ret i32 %call
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}
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; Same thing, using a fixed offset. The load should foid.
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; CHECK: rdar12282281fixed
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; CHECK: jmpq *8(%r11) # TAILCALL
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define i32 @rdar12282281fixed() nounwind uwtable ssp {
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entry:
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%0 = load i32 (i8*, ...)** getelementptr inbounds ([0 x i32 (i8*, ...)*]* @funcs, i64 0, i64 1), align 8
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%call.i = tail call i32 (i8*, ...)* %0(i8* null, i32 0, i32 0, i32 0, i32 0, i32 0) nounwind
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ret i32 %call.i
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}
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