Files
llvm-6502/lib/CodeGen/SelectionDAG
Chad Rosier 92bcd96bbc When pattern matching during instruction selection make sure shl x,1 is not
converted to add x,x if x is a undef.  add undef, undef does not guarantee
that the resulting low order bit is zero.
Fixes <rdar://problem/9453156> and <rdar://problem/9487392>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14 22:29:10 +00:00
..
2011-05-24 18:27:52 +00:00