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https://github.com/c64scene-ar/llvm-6502.git
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46f7257ed1
AMD's processors family K7, K8, K10, K12, K15 and K16 are known to have SHLD/SHRD instructions with very poor latency. Optimization guides for these processors recommend using an alternative sequence of instructions. For these AMD's processors, I disabled folding (or (x << c) | (y >> (64 - c))) when we are not optimizing for size. It might be beneficial to disable this folding for some of the Intel's processors. However, since I couldn't find specific recommendations regarding using SHLD/SHRD instructions on Intel's processors, I haven't disabled this peephole for Intel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195383 91177308-0d34-0410-b5e6-96231b3b80d8
562 lines
18 KiB
C++
562 lines
18 KiB
C++
//===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the X86 specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "subtarget"
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#include "X86Subtarget.h"
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#include "X86InstrInfo.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Host.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "X86GenSubtargetInfo.inc"
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using namespace llvm;
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#if defined(_MSC_VER)
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#include <intrin.h>
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#endif
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/// ClassifyBlockAddressReference - Classify a blockaddress reference for the
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/// current subtarget according to how we should reference it in a non-pcrel
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/// context.
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unsigned char X86Subtarget::ClassifyBlockAddressReference() const {
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if (isPICStyleGOT()) // 32-bit ELF targets.
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return X86II::MO_GOTOFF;
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if (isPICStyleStubPIC()) // Darwin/32 in PIC mode.
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return X86II::MO_PIC_BASE_OFFSET;
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// Direct static reference to label.
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return X86II::MO_NO_FLAG;
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}
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/// ClassifyGlobalReference - Classify a global variable reference for the
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/// current subtarget according to how we should reference it in a non-pcrel
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/// context.
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unsigned char X86Subtarget::
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ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
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// DLLImport only exists on windows, it is implemented as a load from a
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// DLLIMPORT stub.
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if (GV->hasDLLImportLinkage())
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return X86II::MO_DLLIMPORT;
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// Determine whether this is a reference to a definition or a declaration.
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// Materializable GVs (in JIT lazy compilation mode) do not require an extra
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// load from stub.
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bool isDecl = GV->hasAvailableExternallyLinkage();
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if (GV->isDeclaration() && !GV->isMaterializable())
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isDecl = true;
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// X86-64 in PIC mode.
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if (isPICStyleRIPRel()) {
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// Large model never uses stubs.
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if (TM.getCodeModel() == CodeModel::Large)
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return X86II::MO_NO_FLAG;
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if (isTargetDarwin()) {
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// If symbol visibility is hidden, the extra load is not needed if
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// target is x86-64 or the symbol is definitely defined in the current
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// translation unit.
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if (GV->hasDefaultVisibility() &&
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(isDecl || GV->isWeakForLinker()))
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return X86II::MO_GOTPCREL;
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} else if (!isTargetWin64()) {
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assert(isTargetELF() && "Unknown rip-relative target");
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// Extra load is needed for all externally visible.
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if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
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return X86II::MO_GOTPCREL;
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}
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return X86II::MO_NO_FLAG;
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}
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if (isPICStyleGOT()) { // 32-bit ELF targets.
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// Extra load is needed for all externally visible.
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if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
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return X86II::MO_GOTOFF;
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return X86II::MO_GOT;
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}
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if (isPICStyleStubPIC()) { // Darwin/32 in PIC mode.
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// Determine whether we have a stub reference and/or whether the reference
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// is relative to the PIC base or not.
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return X86II::MO_PIC_BASE_OFFSET;
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
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// If symbol visibility is hidden, we have a stub for common symbol
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// references and external declarations.
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if (isDecl || GV->hasCommonLinkage()) {
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// Hidden $non_lazy_ptr reference.
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return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
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}
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// Otherwise, no stub.
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return X86II::MO_PIC_BASE_OFFSET;
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}
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if (isPICStyleStubNoDynamic()) { // Darwin/32 in -mdynamic-no-pic mode.
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// Determine whether we have a stub reference.
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// If this is a strong reference to a definition, it is definitely not
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// through a stub.
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if (!isDecl && !GV->isWeakForLinker())
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return X86II::MO_NO_FLAG;
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// Unless we have a symbol with hidden visibility, we have to go through a
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// normal $non_lazy_ptr stub because this symbol might be resolved late.
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if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
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return X86II::MO_DARWIN_NONLAZY;
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// Otherwise, no stub.
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return X86II::MO_NO_FLAG;
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}
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// Direct static reference to global.
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return X86II::MO_NO_FLAG;
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}
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/// getBZeroEntry - This function returns the name of a function which has an
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/// interface like the non-standard bzero function, if such a function exists on
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/// the current subtarget and it is considered prefereable over memset with zero
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/// passed as the second argument. Otherwise it returns null.
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const char *X86Subtarget::getBZeroEntry() const {
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// Darwin 10 has a __bzero entry point for this purpose.
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if (getTargetTriple().isMacOSX() &&
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!getTargetTriple().isMacOSXVersionLT(10, 6))
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return "__bzero";
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return 0;
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}
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bool X86Subtarget::hasSinCos() const {
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return getTargetTriple().isMacOSX() &&
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!getTargetTriple().isMacOSXVersionLT(10, 9) &&
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is64Bit();
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}
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/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
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/// to immediate address.
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bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
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if (In64BitMode)
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return false;
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return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
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}
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static bool OSHasAVXSupport() {
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#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
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|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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#if defined(__GNUC__)
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// Check xgetbv; this uses a .byte sequence instead of the instruction
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// directly because older assemblers do not include support for xgetbv and
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// there is no easy way to conditionally compile based on the assembler used.
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int rEAX, rEDX;
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__asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
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#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
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unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
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#else
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int rEAX = 0; // Ensures we return false
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#endif
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return (rEAX & 6) == 6;
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#else
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return false;
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#endif
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}
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void X86Subtarget::AutoDetectSubtargetFeatures() {
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unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
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unsigned MaxLevel;
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union {
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unsigned u[3];
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char c[12];
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} text;
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if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
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MaxLevel < 1)
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return;
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X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
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if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
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if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); }
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if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); }
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if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); }
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if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); }
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if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
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if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
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if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
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if (((ECX >> 27) & 1) && ((ECX >> 28) & 1) && OSHasAVXSupport()) {
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X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX);
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}
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bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
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bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
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if ((ECX >> 1) & 0x1) {
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HasPCLMUL = true;
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ToggleFeature(X86::FeaturePCLMUL);
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}
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if ((ECX >> 12) & 0x1) {
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HasFMA = true;
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ToggleFeature(X86::FeatureFMA);
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}
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if (IsIntel && ((ECX >> 22) & 0x1)) {
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HasMOVBE = true;
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ToggleFeature(X86::FeatureMOVBE);
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}
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if ((ECX >> 23) & 0x1) {
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HasPOPCNT = true;
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ToggleFeature(X86::FeaturePOPCNT);
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}
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if ((ECX >> 25) & 0x1) {
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HasAES = true;
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ToggleFeature(X86::FeatureAES);
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}
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if ((ECX >> 29) & 0x1) {
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HasF16C = true;
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ToggleFeature(X86::FeatureF16C);
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}
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if (IsIntel && ((ECX >> 30) & 0x1)) {
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HasRDRAND = true;
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ToggleFeature(X86::FeatureRDRAND);
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}
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if ((ECX >> 13) & 0x1) {
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HasCmpxchg16b = true;
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ToggleFeature(X86::FeatureCMPXCHG16B);
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}
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if (IsIntel || IsAMD) {
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// Determine if bit test memory instructions are slow.
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unsigned Family = 0;
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unsigned Model = 0;
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X86_MC::DetectFamilyModel(EAX, Family, Model);
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if (IsAMD || (Family == 6 && Model >= 13)) {
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IsBTMemSlow = true;
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ToggleFeature(X86::FeatureSlowBTMem);
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}
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// Determine if SHLD/SHRD instructions have higher latency then the
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// equivalent series of shifts/or instructions.
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// FIXME: Add Intel's processors that have SHLD instructions with very
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// poor latency.
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if (IsAMD) {
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IsSHLDSlow = true;
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ToggleFeature(X86::FeatureSlowSHLD);
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}
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// If it's an Intel chip since Nehalem and not an Atom chip, unaligned
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// memory access is fast. We hard code model numbers here because they
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// aren't strictly increasing for Intel chips it seems.
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if (IsIntel &&
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((Family == 6 && Model == 0x1E) || // Nehalem: Clarksfield, Lynnfield,
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// Jasper Froest
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(Family == 6 && Model == 0x1A) || // Nehalem: Bloomfield, Nehalem-EP
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(Family == 6 && Model == 0x2E) || // Nehalem: Nehalem-EX
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(Family == 6 && Model == 0x25) || // Westmere: Arrandale, Clarksdale
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(Family == 6 && Model == 0x2C) || // Westmere: Gulftown, Westmere-EP
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(Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX
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(Family == 6 && Model == 0x2A) || // SandyBridge
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(Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E*
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(Family == 6 && Model == 0x3A))) {// IvyBridge
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IsUAMemFast = true;
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ToggleFeature(X86::FeatureFastUAMem);
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}
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// Set processor type. Currently only Atom or Silvermont (SLM) is detected.
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if (Family == 6 &&
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(Model == 28 || Model == 38 || Model == 39 ||
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Model == 53 || Model == 54)) {
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X86ProcFamily = IntelAtom;
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UseLeaForSP = true;
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ToggleFeature(X86::FeatureLeaForSP);
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}
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else if (Family == 6 &&
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(Model == 55 || Model == 74 || Model == 77)) {
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X86ProcFamily = IntelSLM;
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}
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unsigned MaxExtLevel;
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X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
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if (MaxExtLevel >= 0x80000001) {
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X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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if ((EDX >> 29) & 0x1) {
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HasX86_64 = true;
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ToggleFeature(X86::Feature64Bit);
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}
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if ((ECX >> 5) & 0x1) {
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HasLZCNT = true;
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ToggleFeature(X86::FeatureLZCNT);
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}
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if (IsIntel && ((ECX >> 8) & 0x1)) {
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HasPRFCHW = true;
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ToggleFeature(X86::FeaturePRFCHW);
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}
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if (IsAMD) {
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if ((ECX >> 6) & 0x1) {
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HasSSE4A = true;
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ToggleFeature(X86::FeatureSSE4A);
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}
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if ((ECX >> 11) & 0x1) {
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HasXOP = true;
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ToggleFeature(X86::FeatureXOP);
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}
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if ((ECX >> 16) & 0x1) {
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HasFMA4 = true;
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ToggleFeature(X86::FeatureFMA4);
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}
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}
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}
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}
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if (MaxLevel >= 7) {
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if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
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if (IsIntel && (EBX & 0x1)) {
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HasFSGSBase = true;
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ToggleFeature(X86::FeatureFSGSBase);
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}
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if ((EBX >> 3) & 0x1) {
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HasBMI = true;
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ToggleFeature(X86::FeatureBMI);
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}
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if ((EBX >> 4) & 0x1) {
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HasHLE = true;
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ToggleFeature(X86::FeatureHLE);
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}
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if (IsIntel && ((EBX >> 5) & 0x1)) {
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X86SSELevel = AVX2;
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ToggleFeature(X86::FeatureAVX2);
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}
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if (IsIntel && ((EBX >> 8) & 0x1)) {
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HasBMI2 = true;
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ToggleFeature(X86::FeatureBMI2);
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}
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if (IsIntel && ((EBX >> 11) & 0x1)) {
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HasRTM = true;
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ToggleFeature(X86::FeatureRTM);
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}
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if (IsIntel && ((EBX >> 16) & 0x1)) {
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X86SSELevel = AVX512F;
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ToggleFeature(X86::FeatureAVX512);
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}
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if (IsIntel && ((EBX >> 18) & 0x1)) {
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HasRDSEED = true;
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ToggleFeature(X86::FeatureRDSEED);
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}
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if (IsIntel && ((EBX >> 19) & 0x1)) {
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HasADX = true;
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ToggleFeature(X86::FeatureADX);
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}
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if (IsIntel && ((EBX >> 26) & 0x1)) {
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HasPFI = true;
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ToggleFeature(X86::FeaturePFI);
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}
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if (IsIntel && ((EBX >> 27) & 0x1)) {
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HasERI = true;
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ToggleFeature(X86::FeatureERI);
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}
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if (IsIntel && ((EBX >> 28) & 0x1)) {
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HasCDI = true;
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ToggleFeature(X86::FeatureCDI);
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}
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if (IsIntel && ((EBX >> 29) & 0x1)) {
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HasSHA = true;
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ToggleFeature(X86::FeatureSHA);
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}
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}
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if (IsAMD && ((ECX >> 21) & 0x1)) {
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HasTBM = true;
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ToggleFeature(X86::FeatureTBM);
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}
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}
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}
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void X86Subtarget::resetSubtargetFeatures(const MachineFunction *MF) {
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AttributeSet FnAttrs = MF->getFunction()->getAttributes();
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Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
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"target-cpu");
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Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
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"target-features");
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std::string CPU =
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!CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
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std::string FS =
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!FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
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if (!FS.empty()) {
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initializeEnvironment();
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resetSubtargetFeatures(CPU, FS);
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}
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}
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void X86Subtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
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std::string CPUName = CPU;
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if (!FS.empty() || !CPU.empty()) {
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if (CPUName.empty()) {
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#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
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|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
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CPUName = sys::getHostCPUName();
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#else
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CPUName = "generic";
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#endif
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}
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// Make sure 64-bit features are available in 64-bit mode. (But make sure
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// SSE2 can be turned off explicitly.)
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std::string FullFS = FS;
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if (In64BitMode) {
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if (!FullFS.empty())
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FullFS = "+64bit,+sse2," + FullFS;
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else
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FullFS = "+64bit,+sse2";
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}
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// If feature string is not empty, parse features string.
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ParseSubtargetFeatures(CPUName, FullFS);
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} else {
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if (CPUName.empty()) {
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#if defined (__x86_64__) || defined(__i386__)
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CPUName = sys::getHostCPUName();
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#else
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CPUName = "generic";
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#endif
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}
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// Otherwise, use CPUID to auto-detect feature set.
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AutoDetectSubtargetFeatures();
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// Make sure 64-bit features are available in 64-bit mode.
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if (In64BitMode) {
|
|
if (!HasX86_64) { HasX86_64 = true; ToggleFeature(X86::Feature64Bit); }
|
|
if (!HasCMov) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
|
|
|
|
if (X86SSELevel < SSE2) {
|
|
X86SSELevel = SSE2;
|
|
ToggleFeature(X86::FeatureSSE1);
|
|
ToggleFeature(X86::FeatureSSE2);
|
|
}
|
|
}
|
|
}
|
|
|
|
// CPUName may have been set by the CPU detection code. Make sure the
|
|
// new MCSchedModel is used.
|
|
InitCPUSchedModel(CPUName);
|
|
|
|
if (X86ProcFamily == IntelAtom || X86ProcFamily == IntelSLM)
|
|
PostRAScheduler = true;
|
|
|
|
InstrItins = getInstrItineraryForCPU(CPUName);
|
|
|
|
// It's important to keep the MCSubtargetInfo feature bits in sync with
|
|
// target data structure which is shared with MC code emitter, etc.
|
|
if (In64BitMode)
|
|
ToggleFeature(X86::Mode64Bit);
|
|
|
|
DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
|
|
<< ", 3DNowLevel " << X863DNowLevel
|
|
<< ", 64bit " << HasX86_64 << "\n");
|
|
assert((!In64BitMode || HasX86_64) &&
|
|
"64-bit code requested on a subtarget that doesn't support it!");
|
|
|
|
// Stack alignment is 16 bytes on Darwin, Linux and Solaris (both
|
|
// 32 and 64 bit) and for all 64-bit targets.
|
|
if (StackAlignOverride)
|
|
stackAlignment = StackAlignOverride;
|
|
else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
|
|
In64BitMode)
|
|
stackAlignment = 16;
|
|
}
|
|
|
|
void X86Subtarget::initializeEnvironment() {
|
|
X86SSELevel = NoMMXSSE;
|
|
X863DNowLevel = NoThreeDNow;
|
|
HasCMov = false;
|
|
HasX86_64 = false;
|
|
HasPOPCNT = false;
|
|
HasSSE4A = false;
|
|
HasAES = false;
|
|
HasPCLMUL = false;
|
|
HasFMA = false;
|
|
HasFMA4 = false;
|
|
HasXOP = false;
|
|
HasTBM = false;
|
|
HasMOVBE = false;
|
|
HasRDRAND = false;
|
|
HasF16C = false;
|
|
HasFSGSBase = false;
|
|
HasLZCNT = false;
|
|
HasBMI = false;
|
|
HasBMI2 = false;
|
|
HasRTM = false;
|
|
HasHLE = false;
|
|
HasERI = false;
|
|
HasCDI = false;
|
|
HasPFI = false;
|
|
HasADX = false;
|
|
HasSHA = false;
|
|
HasPRFCHW = false;
|
|
HasRDSEED = false;
|
|
IsBTMemSlow = false;
|
|
IsSHLDSlow = false;
|
|
IsUAMemFast = false;
|
|
HasVectorUAMem = false;
|
|
HasCmpxchg16b = false;
|
|
UseLeaForSP = false;
|
|
HasSlowDivide = false;
|
|
PostRAScheduler = false;
|
|
PadShortFunctions = false;
|
|
CallRegIndirect = false;
|
|
LEAUsesAG = false;
|
|
stackAlignment = 4;
|
|
// FIXME: this is a known good value for Yonah. How about others?
|
|
MaxInlineSizeThreshold = 128;
|
|
}
|
|
|
|
X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
|
|
const std::string &FS,
|
|
unsigned StackAlignOverride, bool is64Bit)
|
|
: X86GenSubtargetInfo(TT, CPU, FS)
|
|
, X86ProcFamily(Others)
|
|
, PICStyle(PICStyles::None)
|
|
, TargetTriple(TT)
|
|
, StackAlignOverride(StackAlignOverride)
|
|
, In64BitMode(is64Bit) {
|
|
initializeEnvironment();
|
|
resetSubtargetFeatures(CPU, FS);
|
|
}
|
|
|
|
bool X86Subtarget::enablePostRAScheduler(
|
|
CodeGenOpt::Level OptLevel,
|
|
TargetSubtargetInfo::AntiDepBreakMode& Mode,
|
|
RegClassVector& CriticalPathRCs) const {
|
|
Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
|
|
CriticalPathRCs.clear();
|
|
return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
|
|
}
|