llvm-6502/lib/Target
Brian Gaeke 9604416192 Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well.
SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
 their fields were totally screwed up. This seems to fix the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6429 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-30 08:02:14 +00:00
..
CBackend Eliminate unnecessary ->get calls that are now automatically handled. 2003-05-29 15:12:27 +00:00
SparcV9 Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well. 2003-05-30 08:02:14 +00:00
X86
Makefile
MRegisterInfo.cpp
Target.td Added the target-independent part of TableGen data. 2003-05-29 18:48:17 +00:00
TargetData.cpp
TargetInstrInfo.cpp
TargetMachine.cpp
TargetSchedInfo.cpp