mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2026-04-27 04:18:42 +00:00
Jingyue Wu
9764983070
Summary: MCRegAliasIterator only works for physical registers. So, do not run it on virtual registers. With this issue fixed, we can resurrect the BranchFolding pass in NVPTX backend. Reviewers: jholewinski, bkramer Subscribers: henryhu, meheff, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11174 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242871 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
545 B
LLVM
25 lines
545 B
LLVM
; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 -disable-cgp | FileCheck %s
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; Disable CGP which also folds branches, so that only BranchFolding is under
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; the spotlight.
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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define void @foo(i32 %x, float* %output) {
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; CHECK-LABEL: .visible .func foo(
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; CHECK-NOT: bra.uni
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; CHECK-NOT: LBB0_
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%1 = icmp eq i32 %x, 1
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br i1 %1, label %then, label %else
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then:
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br label %merge
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else:
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br label %merge
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merge:
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store float 2.0, float* %output
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ret void
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}
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