Chandler Carruth 977aab501d [x86] Expand the target DAG combining for PSHUFD nodes to be able to ...

combine into half-shuffles through unpack instructions that expand the
half to a whole vector without messing with the dword lanes.

This fixes some redundant instructions in splat-like lowerings for
v16i8, which are now getting to be *really* nice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212695 91177308-0d34-0410-b5e6-96231b3b80d8

2014-07-10 09:57:36 +00:00

..

AArch64

[AArch64]Fix an assertion failure in DAG Combiner about concating 2 build_vector.

2014-07-10 03:41:50 +00:00

ARM

ARM: properly lower dllimport'ed global values

2014-07-07 05:18:35 +00:00

CPP

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Generic

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Hexagon

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Inputs

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Mips

[mips][mips64r6] Correct select patterns that have the condition or true/false values backwards

2014-07-09 10:47:26 +00:00

MSP430

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NVPTX

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PowerPC

[PowerPC] Fix testcase regression

2014-07-07 19:41:54 +00:00

R600

R600/SI: Add support for llvm.convert.{to|from}.fp16

2014-07-10 03:22:20 +00:00

SPARC

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SystemZ

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Thumb

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Thumb2

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X86

[x86] Expand the target DAG combining for PSHUFD nodes to be able to

2014-07-10 09:57:36 +00:00

XCore

llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.

2014-07-04 11:58:03 +00:00