Bradley Smith 47c311bafe [ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205878 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-09 14:43:20 +00:00
..
advsimd.s
aliases.s	[ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.	2014-04-09 14:43:11 +00:00
arithmetic-encoding.s
arm64-fixup.s
basic-a64-instructions.s
bitfield-encoding.s	[ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.	2014-04-09 14:42:49 +00:00
branch-encoding.s
crypto.s
diags.s	[ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.	2014-04-09 14:43:11 +00:00
directive_loh.s
elf-relocs.s
fp-encoding.s	[ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu.	2014-04-09 14:43:20 +00:00
large-relocs.s
lit.local.cfg
logical-encoding.s
mapping-across-sections.s
mapping-within-section.s
memory.s
nv-cond.s	[ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL)	2014-04-09 14:42:07 +00:00
separator.s
simd-ldst.s
small-data-fixups.s
spsel-sysreg.s	[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.	2014-04-09 14:43:06 +00:00
system-encoding.s	[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.	2014-04-09 14:42:36 +00:00
tls-modifiers-darwin.s
tls-relocs.s
variable-exprs.s
vector-lists.s	[ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}	2014-04-09 14:41:58 +00:00
verbose-vector-case.s	[ARM64] Add missing 1Q -> 1q vector kind alias	2014-04-09 14:42:01 +00:00